分離閘快閃式記憶體與一般堆疊閘快閃式記憶體相比，擁有高效率高速度的編碼，然而卻因為多擁有一個選擇閘的部分及位元線的金屬接觸窗部分而使得元件不易縮小化。這篇論文提出了一個新型的分離閘快閃式記憶體架構，其擁有垂直式的選擇閘部分，源極端是共用在深N-型井，並且整個元件陣列架構是利用虛擬接地的AND型陣列，使得這個元件可以達到5F2的元件面積，而且具有獨特的彈道式源極端熱電子注入，而同時能達到高密度、高速度的分離閘快閃式記憶體。
這篇論文完整地介紹了這顆新元件，其中包含著完整的元件製程設計，實作流程，以及詳細電性討論。

Split gate flash memory has the advantage of a higher programming current and efficiency than conventional stacked gate flash memories. It has an additional select gate and requires one bit-line contact per cell, therefore cannot easily achieve high storage density, nor can it be easily scaled down. This investigation proposes a novel split gate flash cell with a vertical trenched transistor. Incorporating a unique ballistic hot electron injection mechanism and a trench select gate structure, this cell not only offers high program efficiency, but also is 50% smaller than conventional planar split gate flash memories, which make it more competitive for high-density storage applications. The flash memory cells are best arranged in a virtual ground AND-type array, which is thus called Ballistic injection AND-Type Flash EEPROM (BiAND). The BiAND flash memory cell can be very efficiently and rapidly written by adapting the source side injection operation. Additionally, the sharing select gate effect, that is widening the trenched select transistor increases the programming current and the read current, is also discussed comprehensively.

This thesis introduces the unique flash memory cell with the trenched select transistor. The process flows for fabricating the BiAND flash memory cell are designed, simulated and implemented. The detailed electrical characteristics of the BiAND cell are accurately measured. The cell performance is discussed extensively to evaluate the feasibility of this novel cell.

Abstract i
Acknowledgment ii
List of Contents iii
List of Figures iv
List of Tables vii
1 Introduction 1
2 Split Gate Flash Memory and AND-type Array 4
2.1 Flash Memory Device 4
2.2 Introduction of AND-type Arrays 7
2.3 Conventional Split Gate Flash Memory Cells 9
2.4 Current Status Reviews 14
3 BiAND Flash Memory 31
3.1 Cell Structure 32
3.2 Operation Principles 34
3.3 BiAND Array Architecture 38
4 Experimental Preparation52
4.1 Process Design for Device Fabrication 52
4.2 Process Flow 55
4.3 Investigations on Sample Cross-sections 60
5 Measurement Results and Discussions 69
5.1 Characteristics of BSSI Programming Gate Current 69
5.2 Effects of Process Variations 72
5.3 Sharing Select Gate Design 74
5.4 Flash Memory Characteristics 75
6 Conclusion 97
References 99

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