帳號:guest(3.142.12.170)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):曾俊彥
作者(外文):Tseng, Chun-Yen
論文名稱(中文):應用於動態電壓轉換器中具動態追蹤計算及抖動預測調變之高效能數位控制器設計
論文名稱(外文):A High-Efficiency Digital Controller with Adaptive Tracking Estimation and Predictive Dither Modulation for Dynamic Output Buck Converter
指導教授(中文):黃柏鈞
指導教授(外文):Huang, Po-Chiun
學位類別:博士
校院名稱:國立清華大學
系所名稱:電機工程學系
學號:913921
出版年(民國):100
畢業學年度:99
語文別:英文
論文頁數:101
中文關鍵詞:動態電壓轉換器數位控制數位抖動調變切換式直流電壓轉換器動態追蹤計算可變電壓系統
相關次數:
  • 推薦推薦:0
  • 點閱點閱:45
  • 評分評分:*****
  • 下載下載:0
  • 收藏收藏:0
隨著晶片整合度的提升,功率的消耗問題也越來越嚴重。在諸多節能技術當中,可變電壓技術越來越受到矚目,搭配可變頻率操作,不僅在動態功率消耗得到大幅的降低,連靜態功率消耗和漏電消耗都能得到節省。在可變電壓頻率系統中,除了系統本身必須能夠適應變壓變頻的操作和軟體排程的支援,同時必須有一個可以動態輸出可變電壓的電壓產生器。
與傳統穩壓器比較,電壓產生器除了本身必須具備高效能之外,同時必須具備快速的動態反應速度,特別是電壓追蹤的特性。此外,除了要能抵抗對於系統元件和寄生元件的變異量,更要能夠適應大範圍操作條件的要求。
在這次的研究報告中,我們是採用數位電路的方式去實現可變電壓產生器的控制電路。相較於類比控制,數位控制具備強大的運算功能,能夠實現複雜的控制演算法,不需要額外的電路補償元件,而且數位訊號操作沒有類比電路操作飽和的問題,同時對於切換雜訊的干擾也比較輕微,不過使用數位方式實現要面臨的會是較多的功率消耗。
對於設計的可變電壓器,我們希望能夠具備幾項特性:在穩定狀態時電壓器的切換頻率是定頻操作,主要是定頻操作在頻譜上的雜訊底層值較低,諧波(harmonic)表現是可以選擇的,這對於電磁干擾(EMI)設計的複雜度能大幅降低。穩定精準的靜態輸出,對於系統的變異量要能夠動態調整,接近電壓器物理限制的快速動態反應。
為了達到設計目標,在系統設計上,採用多種模式控制完成動態電壓輸出,在穩壓操作是採用傳統等比、積分、微分控制器,此類控制器除了具備等比積分基本特性,微分控制可以降低反應不及的問題,同時因為控制參數少在硬體實現具備優勢,對於控制器整合度高。在電壓追蹤操作,是採用開迴路的控制方式,利用電感電壓的斜率變化和電容電荷變化量的需求,可以求得理論上最佳的控制法則,但是如果考量到系統元件(如: 輸入電源、輸出負載和電感電容元件) 的變異和元件寄生效應,最佳化的控制方式是無法達成的,為了讓控制能得到有效地提升,在這裡採用觀察輸出變化和對應的控制脈衝變化,去求得有效的控制變化量,然後再去調整控制器裡原有的控制變數。值得一提的是這樣的動態調整機制不需要額外的偵測電路,所需要的訊息都可以在原本的控制迴路裡面得到。控制器可以藉由學習的方式去調整控制器參數,從量測值得知,最差的情況可以由41%的工作表現提升到83%的工作表現。同樣的調整機制也可以用在調整等比、積分、微分控制器,在這類的調整主要是針對系統操作條件(輸入電源)的變異,相較一般穩壓控制由一組控制參數去做反應,從量測值推算,系統頻寬的差異可以由最大100%變到最差只有20%。
在電路實現方面,查找表(look-up table)取代需要高速操作的運算子,另外應用數位抖動的特性發展預測抖動調變,由偵測輸出斜率變化的方式,去決定最低兩位元的控制碼,這樣的方式可以有效的去消除數位實現產生的量化誤差。在介面電路實現部份,主要是類比數位轉換器(ADC)和數位脈衝調變器(DPWM),在我們的應用裡,線性震盪器用來將電壓轉換成頻率,為了配合預測內插的方式,名為接力式(relay-race) 計數器用以支援。具備類似同時運算的能力,等效上來說可以增加類比數位轉換器的輸出量,更重要的是可以在額定時間內獲得更多相關的資訊。接力式計數器由幾個位元數少的計數器所組成,一旦當計數器的計數量為其飽和數值,會有一個指示信號觸發下一個計數器,而目前工作的計數器會在一段時間延遲後重置工作,靜置的計數器可以使用在下一個需要觸發的程序,
這樣的配置可以降低計數單元的複雜度,同時降低電路觸發所需要的功率消耗達原本所需的70%。數位脈衝調變器是採用計數器為基礎的架構,根據所接收到的控制脈衝指令決定所需要的延遲,在這裡是用連續除頻(/2)的方式完成。
除了數位控制迴路,為了讓直流轉換器控制效能提升,在轉換器本身增加了電流偵測器,藉由觀察功率電晶體上的電流變化,判別連續導通模式(CCM)和非連續導通模式(DCM)的操作邊界,以及時修正數位控制器所得到的脈衝寬度,同時保護功率電晶體免於大電流或電壓擾動等物理傷害。
除了電磁元件電感、電容之外,整個系統均被整合在單晶片之中,並使用了0.18μm標準CMOS製程,功率切換元件是採用3.3伏的元件,電壓產生器的切換頻率是1MHz,控制器所需最高頻率為32MHz,由量測值推算現性控制部份的單位增益頻寬約為50KHz,藉由動態調整機制,電壓產生器都能大致維持系統設計的頻寬表現,同樣在動態調整機制的協助之下,電壓追蹤的動態表現約為25μs/V,而在沒有電流限制的情況下,最佳電壓追蹤可以達16μs/V,數位控制電路部份幾乎可以由合成的方式完成,控制器部分的電流消耗在最佳操作條件下約為100μA,電壓產生器的最佳效能在0.35W的輸出可以量到96%,數位控制器包含類比數位轉換器和數位脈衝調變器面積約為0.09mm2,在不含測試電路,控制器電路包含類比保護電路占整體有效面積約15%。
1 SOC Power Management 1
1.1 Power Management for High Efficiency Processor . . . . . . . . . . . . . . . . . . 2
1.2 Overviews of Dynamic Output Switching Converter . . . . . . . . . . . . . . . . . 3
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Digitally Controlled Switching Type DC-DC Converter 5
2.1 Buck Converter Basic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Buck Converter and Characteristic . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 Buck Converter Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Buck Converter with Digital Control Overview . . . . . . . . . . . . . . . . . . . 9
2.3 Design Issues for Digital Controller . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 Quantization Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.2 Digital Time Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.3 Digital Dither Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Buck Converter Control Techniques . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.1 Voltage Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.2 Current Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.3 Advanced Control Techniques . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4.4 Discrete Control Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5 Peripheral Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.5.1 Digital Pulse Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . 34
2.5.2 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . 35
3 System Design for Dynamic Output Digitally Controlled Power Converter 36
3.1 Previous Works for DVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2 Current Profile in Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2.1 Evaluation of Current Signal for Buck Control . . . . . . . . . . . . . . . 37
3.2.2 Practical Issues for Current Sensing . . . . . . . . . . . . . . . . . . . . . 41
3.3 Optimum Operation Points for Switching Power-MOS . . . . . . . . . . . . . . . 43
3.4 Mixed Signal Simulation Environment . . . . . . . . . . . . . . . . . . . . . . . . 44
4 Digital Controller for Dynamic Output Power Converter 47
4.1 System Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2 Transient-Triggered System Adaption . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3 Indirect Current Slop Control with Adaptive Parameter Assignment . . . . . . . . 54
4.4 Operation Sequence under Physical Limitation . . . . . . . . . . . . . . . . . . . 62
5 Digital Controller Realization of Dynamic Output Power Converter 65
5.1 Linear and Nonlinear Control Combination . . . . . . . . . . . . . . . . . . . . . 66
5.2 PID-Like Control Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3 FSM-Based Predictive Dither Modulation . . . . . . . . . . . . . . . . . . . . . . 77
5.4 Relay-Race-Counter Based A/D Converter . . . . . . . . . . . . . . . . . . . . . . 82
5.5 Digital Pulse Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6 Experimental Results 88
7 Conclusion and Future Work 100
7.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
[1] Y.-P. You, C.-Y. Tseng, Y.-H. Huang, P.-C. Huang, T.-T. Hwang and S.-Y. Hsu, “Low-Power
Techniques for Network Security Processors,” IEEE Asia South Pacific Design Automation Conference, Jan. 2005, pp. 355–360.
[2] C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, “A high-throughput low-cost aes processor,” IEEE Commun. Mag., vol. 41, pp. 86–91, Dec. 2003.
[3] J.-H. Hong and C.-W.Wu, “Cellular array modular multiplier for the rsa public-key cryptosystem
based on modified booth’s algorithm,” IEEE Trans. VLSI Syst., vol. 11, pp. 474–484, June 2003.
[4] T. Fujiyoshi et al., “A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic
voltage/frequency scaling ,” IEEE J. Solid-State Circuits, vol. 41, pp. 54–62, Jan. 2006.
[5] M. Nakai et al., “Dynamic voltage and frequency management for a low-power embedded
microprocessor,” IEEE J. Solid-State Circuits, vol. 1, pp. 28–35, Dec. 2005.
[6] T. D. Burd, T. A. Pering, A. J. Stratakos, and R. W. Brodersen, “A dynamic voltage scaled
microprocessor system,” IEEE J. Solid-State Circuits, vol. 35, pp. 1571–1579, Nov. 2000.
[7] G. Wei and M. A. Horowitz, “A low power switching power supply for self-clocked systems,”
in International Symposium on Low Power Electronics and Design, 1996, pp. 313–318.
[8] G. Wei et al., “A variable-frequency parallel I/O interface with adaptive power supply regulation,”
IEEE J. Solid-State Circuits, vol. 35, pp. 298–299, Feb. 2000.
[9] C.-Y. Tseng, L.-W. Wang and P.-C. Huang, “An integrated linear regulator with fast output
voltage transition for dual-supply SRAMs in DVFS systems,” IEEE J. Solid-State Circuits,
vol. 45, pp. 2239–2249, Nov. 2010.
[10] D. Ma, W. H. Ki and C. Y. Tsui, “An integrated one-cycle control buck converter with adaptive
output and dual loops for output error correction,” IEEE J. Solid-State Circuits, vol. 39,
pp. 140–149, Jan. 2004.
[11] P. Y.Wu and K. T. Mok, “A monolithic buck converter with near-optimum reference tracking
response using adaptive-output-feedback,” IEEE J. Solid-State Circuits, vol. 42, pp. 2441–
2450, Nov. 2007.
[12] F. Su, W. H. Ki and C. Y. Tsui, “Ultra fast fixed-frequency hysteretic buck converter with
maximum charging current control and adaptive delay compensation for DVS applications,”
IEEE J. Solid-State Circuits, vol. 43, pp. 815–822, Apr. 2009.
[13] G. Wei and M. A. Horowitz, “A fully digital, energy-efficient, adaptive power-supply regulator,”
IEEE J. Solid-State Circuits, vol. 34, pp. 520–529, Apr. 1999.
[14] A. P. Dancy, R. Amirtharajah, and A. P. Chandrakasan, “High-efficiency multiple-output DCDC
conversion for low-voltage systems,” IEEE Trans. VLSI Syst., vol. 8, pp. 252–263, June
2000.
[15] J. Kim and M. A. Horowitz, “A efficient digital sliding controller for adaptive power-supply
regulation,” IEEE J. Solid-State Circuits, vol. 37, pp. 639–647, May 2002.
[16] Y. K. Chui,W. H. Ki and C. Y. Tsui, “A programmable integrated digital controller for switching
converters with dual-band switching and complex pole-zero compensation,” IEEE J. Solid-
State Circuits, vol. 40, pp. 772–780, Mar. 2005.
[17] A. Soto, P. Alou, and J. A. Cobos, “Nonlinear digital control breaks bandwidth limitations,”
IEEE Applied Power Electronics Conference, Mar. 2006, pp. 724-730.
[18] D. A. and C. A. P., “Ultra low power control circuit for PWM converter,” in Proc. IEEE Power
Electronics Specialists Conference, June 1997, pp. 21–27.
[19] A. Prodic, D. Maksimovic, and R. W. Erickson, “Design and implementation of a digital
PWM controller for a high-frequency switching DC-DC power converter,” in Proc. IEEE Industrial
Electronics Society Conf., 2001, pp. 893–898.
[20] A. Prodic and D. Maksimovic, “Design of a digital PID regulator based on look-up tables
for control of high-frequency DC-DC converters,” IEEE Workshop on Computers in Power
Electronics, 2002, pp. 2342–2348.
[21] B.J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-frequency digital PWM controller
IC for DC-DC converters,” IEEE Transactions on Power Electronics, vol. 18, pp. 438–
446, Jan. 2003.
[22] J. Xiao, A. V. Peterchev, J. Zhang, and S. R. Sanders, “A 4μA quiescent-current dual-mode
digitally controlled buck converter IC for cellular phone applications,” IEEE J. Solid-State
Circuits, vol. 39, pp. 2342–2348, Dec. 2004.
[23] M. He, and J. Xu, “Nonlinear PID in digital controlled buck converters,” IEEE Applied Power
Electronics Conference, Mar. 2007, pp. 1461–1465.
[24] R. W. Erickson and D. Maksimovic, Fundamental of Power Electronics. Kluwer Academic
Publishers, 2000.
[25] Y. Fukuda, T. Inoue, T. Mizoguchi, S. Yatabe, and Y. Tachi, “Planar inductor with ferrite
layers for DC-DC converter,” IEEE Trans. Magn., vol. 39, pp 2057–2061, July 2003.
[26] C. Yoo, “A CMOS buffer without short-circuit power consumption,” IEEE Trans. Circuits
Syst. II, vol. 47, pp. 935–937, Sept. 2000.
[27] A. Stratakos, S. Sanders and R. Brodersen, “A low-voltage CMOS DC-DC converter for a
portable battery-operated system,” IEEE Power Electronics Specialists Conference, June 1994,
pp. 619–626.
[28] V. Yousefzadeh and D. Maksimovic, “Sensorless optimization of dead times in DC-DC converters
with synchronous rectifiers,” IEEE Applied Power Electronics Conference and Exposition,
Mar. 2005, pp. 911–917.
[29] Z. Zhao and A. Prodic, “ Limit-cycle oscillations based auto-tuning system for digitally controlled
DCVDC power supplies,” IEEE Transactions on Power Electronics, vol. 22, pp. 2211–
2222, Nov. 2007.
[30] E. Rogers, “Understant buck power stages in switchmode power supplies,” Application Report,
Texas Instruments Inc., literature number SLVA057.
[31] J. Sun, D. M. Mitchell, M. F. Greuel, P. T. Krein, and R. M. Bass, “Modeling ofPWMconverters
in discontinuous conduction mode-a reexamination,” IEEE Power Electronics Specialists
Conference, May 1998, pp. 615-622.
[32] A. Dancy, and A. P. Chandrakasan, “Ultra low power control circuits for PWM converters,”
IEEE Power Electronics Specialist Conference, June 1997, pp. 21–27.
[33] P. Li, X. Kong, Y. Kang, and J. Chen, “A novel PWM technique in digital control and its application
to an improved DC/DC converter,” IEEE Power Electronics Specialists Conference,
June 2001, pp. 254–259.
[34] B. Miao, R. Zane, and D. Maksimovic, “Automated digital controller design for switching
converters,” IEEE Power Electronics Specialists Conference, June 2005, pp. 2729–2735.
[35] K. Leung, and D. Alfano, “Design and implementation of a practical digitalPWM controller,”
IEEE Applied Power Electronics Conference and Exposition, Mar. 2006, pp 19–23.
[36] H. Hu, V. Yousefzadeh, and D. Maksimovic, “Nonlinear control for improved dynamic response
of digitally controlled DC-DC converters,” IEEE Power Electronics Specialists Conference,
June 2006, pp. 1–7.
[37] P. Athalye, D. Maksimovic, and R. Erickson, “Variable-frequency predictive digital current
mode control,” IEEE Power Electronics Letters, vol. 2, pp. 113–116, Dec. 2004.
[38] H. Peng and D. Maksimovic, “Digital current-mode controller for DC-DC converters,” IEEE
Applied Power Electronics Conference and Exposition, Mar. 2005, pp. 899–905.
[39] G. Feng,W. Eberle, and Y. Liu , “A new digital control algorithm to achieve optimal dynamic
performance in DC-to-DC converters,” IEEE Power Electronics Specialists Conference, June
2005, pp. 2744–2749
[40] A. V. Peterchev and S. R. Sanders, “Quantization resolution and limit cycling in digitally
controlled PWM converters,” IEEE Transactions on Power Electronics, vol. 18, pp. 301–308,
Jan. 2003.
[41] J. Chen, M. Ribeiro, R. Payseo, D. Zhou, J. R. Smith, and K. Kernahan, “DPWM time resolution
requirements for digitally controlled DC-DC converters,” IEEE Applied Power Electronics
Conference and Exposition, Mar. 2006, pp. 19–23.
[42] D. Maksimovic and R. Zane, “Small-signal discrete-time modeling of digitally controlled
PWM converters,” IEEE Trans. Ind. Electron., vol. 22, pp. 2552–2556, Nov. 2007.
[43] H. Peng, A. Prodic, E. Alarcon, and D. Maksimovic, “Modeling of quantization effect in
digitally controlled DC-DC converters,” IEEE Transactions on Power Electronics, vol. 22,
pp. 208–215, Jan. 2007.
[44] K. Lim, C. H. Park and D. S. Kim and B. Kim, “A low-noise phase-locked loop design by
loop bandwidth optimization,” IEEE J. Solid-State Circuits, vol. 35, pp. 807–815, June 2000.
[45] S. Bibian, and J. Hua, “Time delay compensation of digital control for dc switch mode
power supplies using prediction techniques,” IEEE Transactions on Power Electronics, vol. 15,
pp. 835–842, Sept. 2000.
[46] D. Mitchell and B. Mammano, “Design stable control loops,” Application Report, Texas Instruments
Inc., literature number SLUP173.
[47] R. Ridley “A general approach for optimizing dynamic response for buck converter,” Application
Report, ON Semiconductor Inc., literature number AND8143/D.
[48] P. L. Wong, F. C. Lee, P. Wu and K. Yao, “Critical inductance in voltage regulator modules,”
IEEE Transactions on Power Electronics, vol. 17, pp. 485–492, July 2002.
[49] K. Yao, Y. Meng, and F. C. Lee, “Control bandwidth and transient response of buck converters,”
IEEE Power Electronics Specialists Conference, June 2002, pp. 137–142.
[50] G. K. Schoneman, and D. M. Mitchell, “Output impedance considerations for switching regulators
with current-injected control,” IEEE Power Electronics Specialists Conference, June
1987, pp. 324–335.
[51] E. Rogers “A more Accurate current-mode control model,” Application Report, Texas Instruments
Inc., literature number SLUP122.
[52] S. Qu, “Modeling and Design Consideration of V 2 controlled buck regulator,” IEEE Applied
Power Electronics Conference, Mar. 2001, pp. 507-513.
[53] G. F. Franklin, J. D. Powell, and M. L.Workman, Digital control of dynamic system. Addison-
Wesley, 1998.
[54] S. Buso and P. Mattacelli, Digital cotrol in power electronics. Morgan& Claypool Publishers,
2006.
[55] A. V. Peterchev, J. Xiao, S. R. Sanders, “Architecture and IC implementation of a digital
VRM controller,” IEEE Transactions on Power Electronics, vol. 18, pp. 383–391, Jan. 2004.
[56] A. Syed, E. Ahmed, and D. Maksimovic, “Digital pulse width modulator architectures,” IEEE
Power Electronics Specialists Conference, June 2004, pp. 4689–4695.
[57] E. O’Malley, and K. Rinne, “A programmable digital pulse width modulator providing versatile
pulse patterns and supporting switching frequencies beyond 15 MHz,” IEEE Applied
Power Electronics Conference and Exposition, 2004, pp. 53–59.
[58] K.Wang, N. Rahman, Z. Lukic, and A. Prodic, “All-digital DPWM/DPFM controller for lowpower
DC-DC converters,” IEEE Applied Power Electronics Conference, Mar. 2006, pp. 719-
723.
[59] R. Foley, R. Kavanagh, W. Marnane, and M. Egan, “Multiphase digital pulsewidth modulator,” IEEE Transactions on Power Electronics, vol. 21, pp. 842–846, May 2006.
[60] V. Yousefzadeh, T. Takayama, and D. Maksimovi, “Hybrid DPWM with digital delay-locked loop,” IEEE Computers in Power Electronics, pp. 142–148, July 2006.
[61] P.-H. Lan, C.-Y. Tseng, F.-C. Yeh, and P.-C. Huang, “A multi-mode digital controller with windowed ADC and self-calibrated DPWM for slew-enhanced switching converter,” IEEE Asian Solid-State Circuits Conference, Nov. 2010, pp. 57-60.
[62] R. F. Foley, R. C Kavanagh, W. P Marnane, and M. G. Egan, “A versatile digital pulsewidth modulation architecture with area-efficient FPGA implementation,” IEEE Power Electronics Specialists Conference, June 2005, pp. 2609–2619.
[63] S. C. Huerta, A. D. Castro, O. Garcia, and J. A. Cobos, “FPGA based digital pulse width modulator with time resolution under 2 ns,” IEEE Transactions on Power Electronics, vol. 23, pp. 3135–3134, Nov. 2008.
[64] M. G. Batarseh,W. A. Hoor, L. Huang, C. Iannello, I. Batarseh, “Window-masked segmented digital clock manager-FPGA-based digital pulsewidth modulator technique,” IEEE Transactions
on Power Electronics, vol. 24, pp. 2649–2660, Nov. 2009.
[65] A. Parayandeh and A. Prodic, “Programmable analog-to-digital converter for low-power DCDC
SMPS,” IEEE Transactions on Power Electronics, vol. 23, pp. 500–505, Jan. 2008.
[66] H. Hu, V. Yousefzadeh, and D. Maksimovic, “Nonuniform A/D quantization for improved dynamic responses of digitally controlled DC-DC converters,” IEEE Transactions on Power Electronics, vol. 23, pp. 1998–2005, July 2008.
[67] A. Soto, P. Alou, and J. A. Cobos, “Design methodology for dynamic voltage scaling in the
buck converter,” IEEE Applied Power Electronics Conference, Mar. 2005, pp. 263-269.
[68] A. Soto, P. Alou, and J. A. Cobos, “Design concepts and guidelines for VRMs from a power
stage perspective,” IEEE Power Electronics Specialists Conference, June 2004, pp. 2218-2224.
[69] M. Siu, K. T. Mok, K. N. Leung, Y. H. Lai and W. H. Ki, “A voltage-mode PWM buck regulator with end-point prediction,” IEEE Trans. Circuits Syst. II, vol. 53, pp. 294–298, Apr. 2006.
[70] K. S. Leung and S. H. Chung, “Dynamic hysteresis band control of the buck converter with fast transient response,” IEEE Trans. Circuits Syst. II, vol. 52, pp. 398–402, July 2005.
[71] H. P. Forghani-zadeh and G. A. Rincon-Mora, “Current-sensing techniques for DC-DC
(此全文未開放授權)
電子全文
摘要
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *