|
[1] Y.-P. You, C.-Y. Tseng, Y.-H. Huang, P.-C. Huang, T.-T. Hwang and S.-Y. Hsu, “Low-Power Techniques for Network Security Processors,” IEEE Asia South Pacific Design Automation Conference, Jan. 2005, pp. 355–360. [2] C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, “A high-throughput low-cost aes processor,” IEEE Commun. Mag., vol. 41, pp. 86–91, Dec. 2003. [3] J.-H. Hong and C.-W.Wu, “Cellular array modular multiplier for the rsa public-key cryptosystem based on modified booth’s algorithm,” IEEE Trans. VLSI Syst., vol. 11, pp. 474–484, June 2003. [4] T. Fujiyoshi et al., “A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic voltage/frequency scaling ,” IEEE J. Solid-State Circuits, vol. 41, pp. 54–62, Jan. 2006. [5] M. Nakai et al., “Dynamic voltage and frequency management for a low-power embedded microprocessor,” IEEE J. Solid-State Circuits, vol. 1, pp. 28–35, Dec. 2005. [6] T. D. Burd, T. A. Pering, A. J. Stratakos, and R. W. Brodersen, “A dynamic voltage scaled microprocessor system,” IEEE J. Solid-State Circuits, vol. 35, pp. 1571–1579, Nov. 2000. [7] G. Wei and M. A. Horowitz, “A low power switching power supply for self-clocked systems,” in International Symposium on Low Power Electronics and Design, 1996, pp. 313–318. [8] G. Wei et al., “A variable-frequency parallel I/O interface with adaptive power supply regulation,” IEEE J. Solid-State Circuits, vol. 35, pp. 298–299, Feb. 2000. [9] C.-Y. Tseng, L.-W. Wang and P.-C. Huang, “An integrated linear regulator with fast output voltage transition for dual-supply SRAMs in DVFS systems,” IEEE J. Solid-State Circuits, vol. 45, pp. 2239–2249, Nov. 2010. [10] D. Ma, W. H. Ki and C. Y. Tsui, “An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction,” IEEE J. Solid-State Circuits, vol. 39, pp. 140–149, Jan. 2004. [11] P. Y.Wu and K. T. Mok, “A monolithic buck converter with near-optimum reference tracking response using adaptive-output-feedback,” IEEE J. Solid-State Circuits, vol. 42, pp. 2441– 2450, Nov. 2007. [12] F. Su, W. H. Ki and C. Y. Tsui, “Ultra fast fixed-frequency hysteretic buck converter with maximum charging current control and adaptive delay compensation for DVS applications,” IEEE J. Solid-State Circuits, vol. 43, pp. 815–822, Apr. 2009. [13] G. Wei and M. A. Horowitz, “A fully digital, energy-efficient, adaptive power-supply regulator,” IEEE J. Solid-State Circuits, vol. 34, pp. 520–529, Apr. 1999. [14] A. P. Dancy, R. Amirtharajah, and A. P. Chandrakasan, “High-efficiency multiple-output DCDC conversion for low-voltage systems,” IEEE Trans. VLSI Syst., vol. 8, pp. 252–263, June 2000. [15] J. Kim and M. A. Horowitz, “A efficient digital sliding controller for adaptive power-supply regulation,” IEEE J. Solid-State Circuits, vol. 37, pp. 639–647, May 2002. [16] Y. K. Chui,W. H. Ki and C. Y. Tsui, “A programmable integrated digital controller for switching converters with dual-band switching and complex pole-zero compensation,” IEEE J. Solid- State Circuits, vol. 40, pp. 772–780, Mar. 2005. [17] A. Soto, P. Alou, and J. A. Cobos, “Nonlinear digital control breaks bandwidth limitations,” IEEE Applied Power Electronics Conference, Mar. 2006, pp. 724-730. [18] D. A. and C. A. P., “Ultra low power control circuit for PWM converter,” in Proc. IEEE Power Electronics Specialists Conference, June 1997, pp. 21–27. [19] A. Prodic, D. Maksimovic, and R. W. Erickson, “Design and implementation of a digital PWM controller for a high-frequency switching DC-DC power converter,” in Proc. IEEE Industrial Electronics Society Conf., 2001, pp. 893–898. [20] A. Prodic and D. Maksimovic, “Design of a digital PID regulator based on look-up tables for control of high-frequency DC-DC converters,” IEEE Workshop on Computers in Power Electronics, 2002, pp. 2342–2348. [21] B.J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-frequency digital PWM controller IC for DC-DC converters,” IEEE Transactions on Power Electronics, vol. 18, pp. 438– 446, Jan. 2003. [22] J. Xiao, A. V. Peterchev, J. Zhang, and S. R. Sanders, “A 4μA quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications,” IEEE J. Solid-State Circuits, vol. 39, pp. 2342–2348, Dec. 2004. [23] M. He, and J. Xu, “Nonlinear PID in digital controlled buck converters,” IEEE Applied Power Electronics Conference, Mar. 2007, pp. 1461–1465. [24] R. W. Erickson and D. Maksimovic, Fundamental of Power Electronics. Kluwer Academic Publishers, 2000. [25] Y. Fukuda, T. Inoue, T. Mizoguchi, S. Yatabe, and Y. Tachi, “Planar inductor with ferrite layers for DC-DC converter,” IEEE Trans. Magn., vol. 39, pp 2057–2061, July 2003. [26] C. Yoo, “A CMOS buffer without short-circuit power consumption,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 935–937, Sept. 2000. [27] A. Stratakos, S. Sanders and R. Brodersen, “A low-voltage CMOS DC-DC converter for a portable battery-operated system,” IEEE Power Electronics Specialists Conference, June 1994, pp. 619–626. [28] V. Yousefzadeh and D. Maksimovic, “Sensorless optimization of dead times in DC-DC converters with synchronous rectifiers,” IEEE Applied Power Electronics Conference and Exposition, Mar. 2005, pp. 911–917. [29] Z. Zhao and A. Prodic, “ Limit-cycle oscillations based auto-tuning system for digitally controlled DCVDC power supplies,” IEEE Transactions on Power Electronics, vol. 22, pp. 2211– 2222, Nov. 2007. [30] E. Rogers, “Understant buck power stages in switchmode power supplies,” Application Report, Texas Instruments Inc., literature number SLVA057. [31] J. Sun, D. M. Mitchell, M. F. Greuel, P. T. Krein, and R. M. Bass, “Modeling ofPWMconverters in discontinuous conduction mode-a reexamination,” IEEE Power Electronics Specialists Conference, May 1998, pp. 615-622. [32] A. Dancy, and A. P. Chandrakasan, “Ultra low power control circuits for PWM converters,” IEEE Power Electronics Specialist Conference, June 1997, pp. 21–27. [33] P. Li, X. Kong, Y. Kang, and J. Chen, “A novel PWM technique in digital control and its application to an improved DC/DC converter,” IEEE Power Electronics Specialists Conference, June 2001, pp. 254–259. [34] B. Miao, R. Zane, and D. Maksimovic, “Automated digital controller design for switching converters,” IEEE Power Electronics Specialists Conference, June 2005, pp. 2729–2735. [35] K. Leung, and D. Alfano, “Design and implementation of a practical digitalPWM controller,” IEEE Applied Power Electronics Conference and Exposition, Mar. 2006, pp 19–23. [36] H. Hu, V. Yousefzadeh, and D. Maksimovic, “Nonlinear control for improved dynamic response of digitally controlled DC-DC converters,” IEEE Power Electronics Specialists Conference, June 2006, pp. 1–7. [37] P. Athalye, D. Maksimovic, and R. Erickson, “Variable-frequency predictive digital current mode control,” IEEE Power Electronics Letters, vol. 2, pp. 113–116, Dec. 2004. [38] H. Peng and D. Maksimovic, “Digital current-mode controller for DC-DC converters,” IEEE Applied Power Electronics Conference and Exposition, Mar. 2005, pp. 899–905. [39] G. Feng,W. Eberle, and Y. Liu , “A new digital control algorithm to achieve optimal dynamic performance in DC-to-DC converters,” IEEE Power Electronics Specialists Conference, June 2005, pp. 2744–2749 [40] A. V. Peterchev and S. R. Sanders, “Quantization resolution and limit cycling in digitally controlled PWM converters,” IEEE Transactions on Power Electronics, vol. 18, pp. 301–308, Jan. 2003. [41] J. Chen, M. Ribeiro, R. Payseo, D. Zhou, J. R. Smith, and K. Kernahan, “DPWM time resolution requirements for digitally controlled DC-DC converters,” IEEE Applied Power Electronics Conference and Exposition, Mar. 2006, pp. 19–23. [42] D. Maksimovic and R. Zane, “Small-signal discrete-time modeling of digitally controlled PWM converters,” IEEE Trans. Ind. Electron., vol. 22, pp. 2552–2556, Nov. 2007. [43] H. Peng, A. Prodic, E. Alarcon, and D. Maksimovic, “Modeling of quantization effect in digitally controlled DC-DC converters,” IEEE Transactions on Power Electronics, vol. 22, pp. 208–215, Jan. 2007. [44] K. Lim, C. H. Park and D. S. Kim and B. Kim, “A low-noise phase-locked loop design by loop bandwidth optimization,” IEEE J. Solid-State Circuits, vol. 35, pp. 807–815, June 2000. [45] S. Bibian, and J. Hua, “Time delay compensation of digital control for dc switch mode power supplies using prediction techniques,” IEEE Transactions on Power Electronics, vol. 15, pp. 835–842, Sept. 2000. [46] D. Mitchell and B. Mammano, “Design stable control loops,” Application Report, Texas Instruments Inc., literature number SLUP173. [47] R. Ridley “A general approach for optimizing dynamic response for buck converter,” Application Report, ON Semiconductor Inc., literature number AND8143/D. [48] P. L. Wong, F. C. Lee, P. Wu and K. Yao, “Critical inductance in voltage regulator modules,” IEEE Transactions on Power Electronics, vol. 17, pp. 485–492, July 2002. [49] K. Yao, Y. Meng, and F. C. Lee, “Control bandwidth and transient response of buck converters,” IEEE Power Electronics Specialists Conference, June 2002, pp. 137–142. [50] G. K. Schoneman, and D. M. Mitchell, “Output impedance considerations for switching regulators with current-injected control,” IEEE Power Electronics Specialists Conference, June 1987, pp. 324–335. [51] E. Rogers “A more Accurate current-mode control model,” Application Report, Texas Instruments Inc., literature number SLUP122. [52] S. Qu, “Modeling and Design Consideration of V 2 controlled buck regulator,” IEEE Applied Power Electronics Conference, Mar. 2001, pp. 507-513. [53] G. F. Franklin, J. D. Powell, and M. L.Workman, Digital control of dynamic system. Addison- Wesley, 1998. [54] S. Buso and P. Mattacelli, Digital cotrol in power electronics. Morgan& Claypool Publishers, 2006. [55] A. V. Peterchev, J. Xiao, S. R. Sanders, “Architecture and IC implementation of a digital VRM controller,” IEEE Transactions on Power Electronics, vol. 18, pp. 383–391, Jan. 2004. [56] A. Syed, E. Ahmed, and D. Maksimovic, “Digital pulse width modulator architectures,” IEEE Power Electronics Specialists Conference, June 2004, pp. 4689–4695. [57] E. O’Malley, and K. Rinne, “A programmable digital pulse width modulator providing versatile pulse patterns and supporting switching frequencies beyond 15 MHz,” IEEE Applied Power Electronics Conference and Exposition, 2004, pp. 53–59. [58] K.Wang, N. Rahman, Z. Lukic, and A. Prodic, “All-digital DPWM/DPFM controller for lowpower DC-DC converters,” IEEE Applied Power Electronics Conference, Mar. 2006, pp. 719- 723. [59] R. Foley, R. Kavanagh, W. Marnane, and M. Egan, “Multiphase digital pulsewidth modulator,” IEEE Transactions on Power Electronics, vol. 21, pp. 842–846, May 2006. [60] V. Yousefzadeh, T. Takayama, and D. Maksimovi, “Hybrid DPWM with digital delay-locked loop,” IEEE Computers in Power Electronics, pp. 142–148, July 2006. [61] P.-H. Lan, C.-Y. Tseng, F.-C. Yeh, and P.-C. Huang, “A multi-mode digital controller with windowed ADC and self-calibrated DPWM for slew-enhanced switching converter,” IEEE Asian Solid-State Circuits Conference, Nov. 2010, pp. 57-60. [62] R. F. Foley, R. C Kavanagh, W. P Marnane, and M. G. Egan, “A versatile digital pulsewidth modulation architecture with area-efficient FPGA implementation,” IEEE Power Electronics Specialists Conference, June 2005, pp. 2609–2619. [63] S. C. Huerta, A. D. Castro, O. Garcia, and J. A. Cobos, “FPGA based digital pulse width modulator with time resolution under 2 ns,” IEEE Transactions on Power Electronics, vol. 23, pp. 3135–3134, Nov. 2008. [64] M. G. Batarseh,W. A. Hoor, L. Huang, C. Iannello, I. Batarseh, “Window-masked segmented digital clock manager-FPGA-based digital pulsewidth modulator technique,” IEEE Transactions on Power Electronics, vol. 24, pp. 2649–2660, Nov. 2009. [65] A. Parayandeh and A. Prodic, “Programmable analog-to-digital converter for low-power DCDC SMPS,” IEEE Transactions on Power Electronics, vol. 23, pp. 500–505, Jan. 2008. [66] H. Hu, V. Yousefzadeh, and D. Maksimovic, “Nonuniform A/D quantization for improved dynamic responses of digitally controlled DC-DC converters,” IEEE Transactions on Power Electronics, vol. 23, pp. 1998–2005, July 2008. [67] A. Soto, P. Alou, and J. A. Cobos, “Design methodology for dynamic voltage scaling in the buck converter,” IEEE Applied Power Electronics Conference, Mar. 2005, pp. 263-269. [68] A. Soto, P. Alou, and J. A. Cobos, “Design concepts and guidelines for VRMs from a power stage perspective,” IEEE Power Electronics Specialists Conference, June 2004, pp. 2218-2224. [69] M. Siu, K. T. Mok, K. N. Leung, Y. H. Lai and W. H. Ki, “A voltage-mode PWM buck regulator with end-point prediction,” IEEE Trans. Circuits Syst. II, vol. 53, pp. 294–298, Apr. 2006. [70] K. S. Leung and S. H. Chung, “Dynamic hysteresis band control of the buck converter with fast transient response,” IEEE Trans. Circuits Syst. II, vol. 52, pp. 398–402, July 2005. [71] H. P. Forghani-zadeh and G. A. Rincon-Mora, “Current-sensing techniques for DC-DC
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