骨牌式電路(domino logic)是目前最常見的動態邏輯設計，它可以實現高速且低使用空間之電路•但是骨牌式電路因為其天生的構造限制，必須沒有反向邏輯閘(inverter gates)，這代表了骨牌式電路的設計必須移除所有的反向邏輯閘•然而，移除反向邏輯閘意味著部分之邏輯區塊必須要被複製(logic duplication)以同時提供正、反向的信號，這會造成電路空間成本的大幅增加，因此設法複製最少的邏輯區塊是很重要的課題。
在以往的方法中最簡單的方式是以狄摩根定理(De Morgan's law)來進行移除反向邏輯閘，並且進行必要的複製；而後Ruchir Puri提出了設定輸出狀態(output phase assignment)之理論，它可以進一步降低了複製邏輯閘的數量。
我們的研究是以迴圈的角度來觀察反向邏輯閘為何不能利用狄摩根定理來移除，並且進一步把整個邏輯電路轉換成一個簡單的抽象圖形。並且利用找出圖形中所有擁有奇數個反向邏輯閘之簡單迴圈，來公式化這個問題，我們的作法能夠完全涵蓋設定輸出狀態理論，且較為容易理解。最後我們將每個這種迴圈當成一個二元條款(boolean clause)，並且將如何符合這些二元條款視為一個加權含蓋問題(weighted covering problem)。然後我們利用啟發式(heuristic)的方法來找出複製最少的邏輯區塊之較佳解。
實驗結果顯示使用我們的複製方法比利用狄摩根定理推演並進行必要複製的方法減少約14%的複製成本，也較Ruchir Puri利用設定輸出狀態(output phase assignment)方式之結果為佳。

Domino logic is one of the most popular dynamic circuit configurations for implementing high-performance and small-area logic designs. Since domino logic is inherently non-inverting, it presents a fundamental constraint of implementing logic functions without any intermediate inversions. Removal of inter-mediate inverters requires logic duplication for generating both the negative and positive signal phases, which results in significant area overhead. Therefore, it is important topic to minimize logic duplication for making a circuit inverter-free.
In previous work, it is simply duplicating all the multi-fanouts nets on the way of pushing all the inverters to the primary inputs by De Morgan’s law called non-optimized logic duplication. Then, Ruchir Puri proposed the area overhead can be substantially reduced by selecting an optimal output phase assignment.
In this paper, we present a previously unaddressed cycle-based logic optimization for minimum area duplication in dynamic logic synthesis. We formulated this problem as finding all the simple cycles with odd inverters in an undirected graph and then there is a constraint formula is made for representing these cycles. Satisfying this formula could be taken as an unate weighted covering problem. In addition, this paper also presents a heuristic algorithm for solving the unate boolean constraint formula.
Our experiment results show that in average there is about 14% improvement from the non-optimized logic duplication; moreover, they are also better than the results using the output phase assignment.

1.Introduction...1
2.Previous work and motivation...3
3.Cycle-based logic optimization...7
3.1 Inverters trapped in cycles...7
3.2 Finding all cycles with trapped inverters...15
3.3 Heuristic solution...27
3.4 Duplication...36
4.Experimental results...41
5.Conclusions and future works...43
Bibliography...44
Appendixes A...46
A.1 Making the test files ...46
A.2 Verification ...48

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