本研究針對先進晶圓級封裝技術(wafer level package, WLP)之改良與設計概念進行討論，焊錫接點位置應力釋放(solder joint stress release)與電子元件訊號扇出(IC signal fan-out)能力為選定之主要設計目標；研究中提出適用於新型電子封裝結構之相關基本理論與可靠度分析技術，並使用發展之電遷移(electromigration)試驗方法尋找新型態晶片封裝技術對其內埋電子元件電遷移現象可能造成之影響。

參考規劃之設計目標，分別使用兩種先進封裝技術作為測試載具並輔助研究進行；其中在具有錫球保護特性之晶圓級封裝(solder joint protection wafer level package, SJP-WLP)中，使用一位於介電層與晶片間之剝離界面達到釋放焊錫接點處累積應力之目的；另一方面，嵌板式封裝(panel base package, PBP)其在選定之嵌板材料上方完成封裝程序，可同時擁有釋放焊錫接點位置應力與扇出電子元件訊號兩項特性。在新型封裝技術中可能使用異於傳統之封裝材料與結構設計，其發生之熱-機械力學行為亦可能不同，藉由本研究中提出之相關分析方法，可針對包括焊錫接點、封裝結構內金屬導線、以及半導體元件中後段製程導線(back end of line, BEOL)進行可靠度評估。針對金屬導線疲勞模型中之疲勞係數求取，可利用有限元素分析方法搭配封裝體可靠度實驗獲得，達到預估金屬導線於溫度循環負載下疲勞壽命之目的；另，利用四點彎矩設備(four-point bending apparatus)可對電遷移實驗中之測試線路直接施加機械應力，研究中藉由此一方式討論先進封裝設計對其內埋元件中後段製程導線電遷移破壞行為可能產生之影響；實驗結果顯示外加機械應力分別僅對鋁/矽/銅與銅金屬導線對應之平均壽命(MTTF)造成有限之影響，然而該數值變化可能導致在布雷克方程式(Black’s equation)中參數求取過程發生誤差，藉由控制金屬導線內部殘餘應力使其位於該結構之抗拉降伏強度(tensile yielding strength)與抗壓降伏強度(compressive yielding strength)之中間值，預期將可提高金屬導線之抗電遷移能力並降低機械應力對使用布雷克方程式時所可能產生之影響；另，具有較強機械強度之金屬導線可降低應力導致孔洞遷移(stress-induced voiding)之發生，亦為建議之導線設計方向。

本研究中提出適用於先進電子封裝技術之分析流程，藉由適當測試載具之驗證，其可達到輔助先進晶圓級封裝設計、結構可靠度分析，以及電遷移效應評估之目的；因此，其內容可作為電子封裝領域研究人員發展新型態封裝技術時之重要參考。

In this research, the improvements and design concepts of advanced wafer level package (WLP) are studied. Two major targets, the solder joint stress release and the integrated circuit (IC) signal fan-out, are especially focused. Due to the demands of the suitable analytic methods applied on the reliability assessment of advanced microelectronic packages, the related fundamental theories and testing approaches are proposed. In addition, the electromigration performance of the embedded IC related to the applied new packaging designs is examined by the presented experiment.

Based on the objective design concepts, two types of novel packaging structures are fabricated to assist the investigation. One idea, the solder joint protection WLP (SJP-WLP), is developed by applying a delaminating layer interposed between the lowest insulation layer and the top surface of the silicon chip. Besides, the panel base package (PBP), which is fabricated on a selected panel material, is also designed to achieve both the capabilities of solder joint stress release and IC signal fan-out. Because of the applied new packaging materials and structures in advanced microelectronic packages, the thermal-mechanical behaviors are different from the conventional cases. By using the established analytic methods, the reliability assessment of solder joints, redistribution lines, and the back end of line (BEOL) of IC devices are studied. The fatigue parameters in prediction model are determined through the FE analysis and the related experiment. Therefore, the lifetime of metal traces under temperature cycling test can be predicted through the FE analysis together with the fatigue model. Besides, the four-point bending apparatus is used to directly impose mechanical loading on testing metal wires, and the influence from packaging designs on electromigration damage is studied. From the results, the applied mechanical stress has a small but finite effect on the MTTF of the Al/Si/Cu and Cu metal lines. However, this variation may lead to an error estimation when calculating the unknowns in the Black's equation. To improve the electromigration reliability and reduce the effects of the mechanical stress on the application of the Black's equation, the residual stress is suggested to be controlled to the mid-value between the compressive and the tensile yielding strength of the metal lines. In addition, metal lines with larger yielding strength are also favorable due to their better resistance of stress-induced voiding (SIV).

The analytic procedures which are suitable for future microelectronic packages are proposed in this research. By means of the validation on the testing specimens, they can be applied well on the design, structural reliability assessment, and electromigration evaluation of the advanced WLP. To develop the advanced microelectronic packages, this research could be quoted as an important reference by the packaging engineers.

ABSTRACT (CHINESE) І
ABSTRACT ІІІ
ACKNOWLEDGEMENT V
TABLE OF CONTENTS VІІ
LIST OF TABLES XІ
LIST OF FIGURES XІІ

CHAPTER 1 INTRODUCTION 1
1.1 Motivation of Research 1
1.2 Literature Survey 3
1.2.1 Wafer Level Package Design and Solder Joint Reliability Prediction 3
1.2.2 Ball Shear Strength Test in Microelectronic Package 9
1.2.3 Electromigration-Induced Failure in Microelectronic Devices 10
1.2.4 Stress Measurement of Metal Thin Film 17
1.2.5 Stress-Induced Voiding in Metallization 20
1.2.6 Effect of Mechanical Stress on Electromigration 23
1.3 Goal of Research 27

CHAPTER 2 FUNDAMENTAL THEORIES 29
2.1 Fundamental Theories of Electronic Packaging Reliability Assessment 29
2.1.1 Solder Joint Reflow Profile Prediction 30
2.1.2 Hardening Rule of Materials 31
2.1.3 Numerical Method and Convergence Criteria 32
2.1.4 Solder Joint Thermal Fatigue Life Prediction 33
2.1.5 Trace Line Thermal Fatigue Life Prediction 36
2.1.6 Contact Theory in Finite Element Analysis 40
2.1.7 Principal of Macro-Micro Modeling Methodology in Finite Element Analysis 42
2.2 Electromigration Mechanism and Failure Time Prediction in Metallization 43
2.2.1 Diffusion and Atom Movement in a Solid 44
2.2.2 The Driving Force of Electromigration 45
2.2.3 Effect of Stress on Electromigration 46
2.2.4 Mean Time to Failure Prediction 48
2.3 Stress-Induced Voiding Mechanism 51
2.4 Factorial Design and Analysis of Variance 54
2.5 Weibull Statistic Analysis for Experimental Data 57

CHAPTER 3 FABRICATION OF TESTING SAMPLES AND EXPERIMENTAL DESIGN OF ELECTROMIGRATION TEST 60
3.1 Sample of Wafer Level Package with a Novel Delaminating Protection Mechanism 61
3.2 Sample of Advanced Panel Base Package Technology 63
3.3 Experimental Setup for Electromigration Test 65
3.3.1 Metal Thin Film Preparation 66
3.3.2 Joule Heating and TCR Measurement 67
3.3.3 Electromigration Test under Applied Mechanical Stress 68

CHAPTER 4 RELIABILITY ASSESSMENT FOR SOLDER JOINT PROTECTION WAFER LEVEL PACKAGE 72
4.1 Finite Element Modeling and Experimental Validation 72
4.2 Finite Element Based Reliability Analysis 75
4.3 Parametric Analysis of Solder Joint Protection Wafer Level Package 78

CHAPTER 5 RELIABILITY ASSESSMENT FOR ADVANCED PANEL BASE PACKAGE TECHNOLOGY 81
5.1 Ball Shear Strength Test for Solder Joints in Panel Base Package 82
5.1.1 Solder on Polymer Structure Description and Finite Element Model 83
5.1.2 Experimental Validation and Effects of Solder on Polymer Structure 85
5.1.3 Effects of Interfacial Adhesive Strength and Redistribution Lines 86
5.2 Reliability Assessment Using Macro-Micro Modeling Methodology 87
5.2.1 Macro-Level Finite Element Model Based Analysis 89
5.2.2 Micro-Level Finite Element Model Based Analysis 91
5.2.3 Comparison of Analytic Results between Ball Shear Strength Test and Board-Level Finite Element Analysis 93
5.3 Reliability Assessment Using Finite Element Model with Designed Redistribution Lines 94
5.3.1 Packaging Thermal Fatigue Life Prediction and Experimental Validation 95
5.3.2 Trace Line Failure Analysis in Thermal Cycling Test 97
5.4 Reliability Assessment for Packages with Two Metal Layers 101
5.4.1 Finite Element Model and Thermo-Mechanical Analysis in Package-Level 102
5.4.2 Geometric Parameters Sensitivity Analysis 105

CHAPTER 6 EFFECT OF MECHANICAL STRESS ON ELECTROMIGRATION- INDUCED FAILURE 108
6.1 Experimental Procedures 108
6.2 Prediction of the Original Residual Stress in Metal Lines 110
6.3 Four-point Bending Tooling Design and Mechanical Loading Estimation 111
6.4 Electromigration Test of Al/0.5Si/1Cu and Cu Metal Lines 112
6.5 Electromigration Test under Applied Mechanical Stress 114
6.6 Parameter Determination for Black's Equation 116
6.7 Summary and Discussion 120

CHAPTER 7 CONCLUSIONS AND RECOMMENDATIONS 123
7.1 Conclusions 123
7.2 Recommendations and Future Works 124

REFERENCES 126
TABLES 149
FIGURES 156

1. A. Badihi, “Ultrathin wafer level chip size package,” IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, pp. 212-214, 2000.
2. R. Tummala, “Fundamentals of Microsystems Packaging,” McGraw-Hill, New York, 2001.
3. P. Garrou, “Wafer Level Chip Scale Packaging (WL-CSP): An Overview,” IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, pp. 198-205, 2000.
4. J. H. Lau, “Flip Chip Technologies,” McGraw-Hill, New York, 1995.
5. J. H. Lau, C. Chang, and R. S. W. Lee, “Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies,” IEEE Transactions on Components and Packaging Technologies, Vol. 24, No. 2, pp. 285-292, 2001.
6. K. N. Chiang, Z. N. Liu, and C. T. Peng, ”Parametric reliability analysis of no-underfill flip chip package,” IEEE Transactions on Components and Packaging Technologies, Vol. 24, No. 4, pp. 635-640, 2001.
7. J. H. Lau, “Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability,” IEEE Transactions on Electronics Packaging Manufacturing, Vol. 25, No. 1, pp. 42-50, 2002.
8. J. H. Lau and R. S. W. Lee, “Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP),” IEEE Transactions on Components and Packaging Technologies, Vol. 25, Issue: 1, pp. 3-14, 2002.
9. A. Mertol, “Stress Analysis and Thermal Characterization of a High Pin Count PQFP,” Journal of Electronic Packaging, Vol. 114, pp. 211-220, 1992.
10. Y. T. Lin, C. T. Peng, and K. N. Chiang, “Parametric Design and Reliability analysis of WIT Wafer Level Packaging,” ASME Transactions on Journal of Electronic Package, Vol. 124, 2002.
11. J. H. Lau, “Ball Grid Array Technology,” McGraw-Hill, New York, 1995.
12. J. Y. Kim, I. S. Kang, M. G. Park, J. H. Kim, S. J. Cho, I. S. Park, and H. S. Chun, “Characterization of Wafer Level Package for Mobile Phone Application,” Proc. of the 51st Electronic Components and Technology Conference, pp. 1-4, 2001, Orlando, USA.
13. D. H. Kim, P. Elenius, and S. Barrett, “Solder Joint Reliability and Characteristics of Deformation and Crack Growth of Sn-Ag-Cu Versus Eutectic Sn-Pb on a WLP in a Thermal Cycling Test,” IEEE Transactions on Electronics Packaging Manufacturing, Vol. 25, No. 2, pp. 84-90, 2002.
14. J. H. Lau and Y. H. Pao, “Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies,” McGraw-Hill, New York, pp. 29-32, 1997.
15. S. H. Dai and M. O. Wang, “Reliability Analysis in Engineering Applications,” Van NosTrand Reinhold, New York, pp. 337-397, 1992.
16. N. R. Mann, R. E. Schafer, and N. D. Singpurwalla, “Methods for Statistical Analysis of Reliability and Life Data,” John Wiley & Sons, New York, pp. 184-258, 1974.
17. L. F. Coffin, “A Study of the Effects of Cyclic Thermal Stress on a Ductile Metal,” Transactions of ASME, Vol. 76, pp. 931-950, 1954.
18. S. S. Manson, “Thermal Stress and Low Cycle Fatigue,” McGraw-Hill, New York, pp. 125-192, 1966.
19. H. D. Solomon, “Fatigue of 60/40 Solder,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-9, pp. 91-104, 1986.
20. X. Q. Shi, H. L. J. Pang, W. Zhou, and Z. P. Wang, “Low Cycle Fatigue Analysis of Temperature and Frequency Effects in Eutectic Solder Alloy,” International Journal of Fatigue, Vol. 22, pp. 217-228, 2000.
21. V. Gektin, A. Bar-Cohen, and J. Ames, “Coffin-Manson Fatigue Model of Underfilled Flip-Chips,” IEEE Transactions on Components, Packaging, and Manufacturing Technology- Part A, Vol. 20, No. 3, pp. 317-326, 1997.
22. J. H. Lau, “Experimental and Analytical Studies of 28-pin Thin Small Outline Package (TSOP) Solder-Joint Reliability,” ASME Transactions on Journal of Electronic Package, Vol. 114, pp. 169-176, 1992.
23. R. Satoh, K. Arakawa, M. Harada, and K. Matsui, “Thermal Fatigue Life of Pb-Sn Alloy Interconnections,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 14, No. 1, pp. 224-232, 1991.
24. J. P. Clech, “BGA, Flip-Chip and CSP Solder Joint Reliability: of the Importance of Model Validation,” Proc. of InterPACK’99, pp.112-121, 1999, Hawaii, USA.
25. J. H. Lau, R. S. W. Lee, and C. Chang, “Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis,” ASME Journal of Electronic Packaging, Vol. 122, No. 4, pp. 311-316, 2000.
26. X. Q. Shi, Z. P. Wang, W. Zhou, H. L. J. Pang, and Q. J. Yang, “A New Creep Constitutive Model for Eutectic Solder Alloy,” ASME Journal of Electronic Packaging, Vol. 124, No. 2, pp. 85-90, 2002.
27. S. J. Ham and S. B. Lee, “Measurement of Creep and Relaxation Behaviors of Wafer-Level CSP Assembly Using Moir□ Interferometry,” ASME Journal of Electronic Packaging, Vol. 125, No. 2, pp. 282-288, 2003.
28. G. Massiot and C. Munier, “A review of creep fatigue failure models in solder material - simplified use of a continuous damage mechanical approach,” Proc. of the 5th EuroSimE, pp. 465-472, 2004, Brussels, Belgium.
29. S. Knecht and L. R. Fox, “Constitutive relation and creep-fatigue life model for eutectic tin-lead solder,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 13, No. 2, pp. 424-433, 1990.
30. M. Sakurai, H. Shibuya, and J. Utsunomiya, “FEM Analysis of Flip-Chip Type BGA,” Proc. of IEEE/CPMT International Electronics Manufacturing Technology Symposium, pp. 131-136, 1998, Berlin, Germany.
31. J. H. Lau, “Experimental and Analytical Studies of 28-pin Thin Small Outline Package (TSOP) Solder-Joint Reliability,” ASME Journal of Electronic Packaging, Vol. 114, pp. 169-176, 1992.
32. R. Darveaux, K. Banerji, A. Mawer, and G. Dody, “Reliability of Plastic Ball Grid Array Assembly,” McGraw-Hill, New York, pp. 379-442, 1995.
33. R. Darveaux, “Effect of Simulation Methodology on Solder Joint Crack Growth Correlation,” Proc. of the 50th Electronic Components and Technology Conference, pp. 1048-1058, 2000, Las Vegas, USA.
34. R. Darveaux, “Effect of Simulation Methodology on Solder Joint Crack Growth Correlation and Fatigue Life Prediction,” ASME Journal of Electronic Packaging, Vol. 124, No. 3, pp. 147-154, 2002.
35. S. Vaynman and S. A. McKeown, “Energy-Based Methodology for the Fatigue Life Prediction of Solder Material,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 16, No. 3, pp. 317-322, 1993.
36. V. Sarihan, “Energy Based Methodology for Damage and Life Prediction of Solder Joints under Thermal Cycling,” Proc. of the 43rd Electronic Components and Technology Conference, pp. 32-38, 1993, Orlando, USA.
37. A. Yeo, C. Lee, and J. H. L. Pang, “Flip Chip Solder Joint Fatigue Life Model Investigation,” Proc. of the 4th Electronics Packaging Technology Conference, pp. 107-114, 2002, Singapore.
38. L. Zhang, R. Sitaraman, V. Patwardhan, L. Nguyen, and N. Kelkar, “Solder Joint Reliability Model with Modified Darveaux’s Equations for the Micro SMD Wafer Level-Chip Scale Package Family,” Proc. of the 53rd Electronic Components and Technology Conference, pp. 572-577, 2003, New Orleans, USA.
39. L. Zhang, V. Arora, L. Nguyen, and N. Kelkar, “Numerical and Experimental Analysis of Large Passivation Opening for Solder Joint Reliability Improvement of Micro SMD Packages,” Journal of Microelectronics Reliability, Vol. 44, pp. 533-541, 2004.
40. C. T. Peng, C. M. Liu, J. C. Lin, H. C. Cheng, and K. N. Chiang, “Reliability Analysis and Design for the Fine-pitch Flip Chip BGA Packaging,” IEEE Transactions on Components and Packaging Technologies, Vol. 27, No. 4, pp. 684-693, 2004.
41. K. A. Brakke, “The Surface Evolver,” Experimental Mathematics, Vol. 1, No. 2, pp. 141-165, 1992.
42. K. A. Brakke, “The Surface Evolver and the Stability of Liquid Surface,” Philosophical Transactions: Mathematical, Physical and Engineering Sciences, Vol. 354, pp. 2143-2157, 1996.
43. S. M. Heinrich, M. Schaefer, S. A. Schroeder, and P. S. Lee, “Prediction of Solder Joint Geometries in Array-Type Interconnects,” ASME Transactions on Journal of Electronic Packaging, Vol. 118, No. 3, pp. 114-121, 1996.
44. K. N. Chiang and W. L. Chen, “Electronic Packaging Reflow Shape Prediction for the Solder Mask Defined Ball Grid Array,” ASME Transactions on Journal of Electronic Packaging, Vol. 120, No. 2, pp. 175-178, 1998.
45. M. J. Pfeifer, “Solder Bump Size and Shape Modeling and Experimental Validation,” IEEE Transactions on Components, Packaging, and Manufacturing Technology - Part B, Vol. 20, No. 4, pp. 452-457, 1997.
46. K. N. Chiang and C. A. Yuan, “An Overview of Solder Bump Shape Prediction Algorithms with Validations,” IEEE Transactions on Advanced Packaging, Vol. 24, No. 2, pp. 158-162, 2001.
47. C. T. Peng, K. N. Chiang, T. Ku, and K. Chang, “Design, Fabrication and Comparison of Lead-Free/Eutectic Solder Joint Reliability of Flip Chip Package,” Proc. of the 5th EuroSimE, pp. 149-156 2004, Brussels, Belgium.
48. J. H. Lau and R. S. W. Lee, “Chip Scale Package, CSP: Design, Material, Processes, and Applications,” McGraw-Hill, Singapore, 1999.
49. C. C. Lee, H. C. Liu, and K. N. Chiang, “3D Structure Design and Reliability Analysis of Wafer Level Package with Bubble-Like Stress Buffer Layer,” Proc. of the 9th ITHERM, pp. 317-324, 2004, Las Vegas, USA.
50. T. Kawahara, “SuperCSPTM,” IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, pp. 215-219, 2000.
51. J. H. Lau, “Low Cost Flip Chip Technologies: for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill,” New York, pp. 344-348, 2000.
52. Q. Zhu, L. Ma, and S. K. Sitaraman, “beta-Helix: a lithography-based compliant off-chip interconnect,” IEEE Transactions on Components and Packaging Technology, Vol. 26, No. 3, pp. 582-590, 2003.
53. Q. Zhu, L. Ma, and S. K. Sitaraman, “Design Optimization of One-Turn Helix: A Novel Compliant Off-Chip Interconnect,” IEEE Transactions on Advanced Packaging, Vol. 26, No. 2, pp. 106-112, 2003.
54. M. Gonzalez, B. Vandevelde, M. V. Bulcke, C. Winters, E. Beyne, Y. J. Lee, L. Larson, B. R. Harkness, M. Mohamed, H. Meynen, and E. Vanlathem, “An Analysis of the Reliability of a Wafer Level Package (WLP) Using a Silicone Under the Bump (SUB) Configuration.” Proc. of the 53th Electronic Components and Technology Conference, pp. 857-863, 2003, New Orleans, USA.
55. F. X. Che, T. H. Low, H. L. Pang, W. C. Lin, C. L. Chiang, and T. K. Yang, “Modeling Thermo-Mechanical Reliability of Bumpless Flip Chip Package,” Proc. of the 54th Electronic Components and Technology Conference, pp. 421-426, 2004, Las Vegas, USA.
56. R. Dudek, H. Walter, R. Doering, and B. Michel, “Thermo-mechanical Design of Resilient Contact Systems for Wafer Level Packaging,” Proc. of the 7th EuroSimE, pp. 173-179, 2006, Como (Milano), Italy.
57. D. C. Montgomery, “Design and Analysis of Experiments, 5th edition,” John Willy and Sons, New York, 2001.
58. C. A. Yuan, C. N. Han, M. C. Yew, C. Y. Chou, and K. N. Chiang, “Design, Analysis and Development of Novel Three-Dimensional Stacking WLCSP,” IEEE Transactions on Advanced Packaging, Vol. 28, No. 3, pp. 387-396, 2005.
59. W. D. van Driel, G. Q. Zhang, J. H. J. Janssen, and L. J. Ernst, “Response Surface Modeling For Nonlinear Packaging Stresses,” Journal of Electronic Packaging, Vol. 125, No. 4, pp. 490-497, 2003.
60. C. C. Chiu, C. J. Wu, C. T. Peng, K. N. Chiang, T. Ku, and K. Cheng, “Reliability Analysis and Factorial Design of Lead-Free Flip Chip Package Using THE Finite Element Method,” Proc. of InterPACK’05, 2005, San Francisco, USA.
61. B. Vandevelde, E. Beyne, G. Q. Zhang, J. Caers, D. Vandepitte, and M. Baelmans, “Parameterized Modeling of Thermomechanical Reliability For CSP Assemblies,” Journal of Electronic Packaging, Vol. 125, No. 4, pp. 498-505, 2003.
62. R. Erich, R. J. Coyle, G. M. Wenger, and A. Primavera, “Shear testing and failure mode analysis for evaluation of BGA ball attachment,” Proc. of the 24th Electronics Manufacturing Technology Symposium, pp. 16-22, 1999, Austin, USA.
63. R. J. Coyle and P. P. Solan, “The influence of test parameters and package design features on ball shear test requirements,” Proc. of the 25th Electronics Manufacturing Technology Symposium, USA, pp. 168-177, 2000, Santa Clara.
64. R. S. W. Lee, C. C. Yan, Z. Karim, and X. Huang, “Assessment on the effects of electroless nickel plating on the reliability of solder ball attachment to the bond pads of PBGA substrate,” Proc. of the 50th Electronic Components and Technology Conference, pp. 868-873, 2000, Las Vegas, USA.
65. C. H. Zhong, S. Yi, Y. C. Mui, C. P. Howe, D. Olsen, and W. T. Chen, “Missing solder ball failure mechanisms in plastic ball grid array packages,” Proc. of the 50th Electronic Components and Technology Conference, pp. 151-159, 2000, Las Vegas, USA.
66. “BGA Ball Shear,” JESD22-B117, JEDEC Standard, Solid State Technology Association, Arlington, USA, 2000.
67. R. S. W. Lee and X. Huang, “Analysis on solder ball shear testing conditions with a simple computational model,” Soldering and Surface Mount Technology, Vol. 14, No. 1, pp. 45-48, 2002.
68. K. C. Chang and K. N. Chiang, “Solder joint reliability analysis of a wafer-level CSP assembly with Cu studs formed on solder pads,” Journal of Chinese Institute of Engineers, Vol. 26, No. 4, pp. 467-479, 2003.
69. K. C. Chang and K. N. Chiang, “Improvements of Solder Ball Shear Strength of a Wafer-Level CSP Using a Novel Cu Stud Technology,” IEEE Transactions on Components and Packaging Technologies, Vol. 27, No. 2, pp. 373-382, 2004.
70. M. C. Yew, C. Y. Chou, C. S. Huang, W. K. Yang, and K. N. Chiang, “The Solder on Rubber (SOR) Interconnection Design and Its Reliability Assessment Based on Shear Strength Test and Finite Element Analysis,” Microelectronic Reliability, Vol. 46, No. 9-11 , pp. 1874-1879, 2006.
71. C. L. Yeh and Y. S. Lai, “Insights Into Correlation Between Board-Level Drop Reliability and Package-Level Ball Impact Test Characteristics,” IEEE Transactions on Electronics Packaging Manufacturing, Vol. 30, No. 1, pp. 84-91, 2007.
72. A. B. Chaudhary and K. J. Bathe, “A Solution Method for Static and Dynamic Analysis of Three-Dimensional Contact Problems with Friction,” Computers & Structures, Vol. 24, No. 6, pp. 855-873, 1986.
73. H. Rothert, H. Idelberger, W. Jacobi, and L. Niemann, “On Geometrically Nonlinear Contact Problems with Friction,” Computer Methods in Applied Mechanics and Engineering, Vol. 51, pp. 139-155, 1985.
74. Y. Kanto and G. Yagawa, “A Dynamic Contact Buckling Analysis by Penalty Finite Element,” International Journal for Numerical Method in Engineering, Vol. 29, pp. 755-774, 1990.
75. J. T. Oden and N. Kikuchi, “Finite Element Methods for Constrained Problems in Elasticity,” International Journal for Numerical Method in Engineering, Vol. 18, pp. 701-725, 1982.
76. G. Yagawa and H. Hirayama, “A Finite Element Method for Contact Problems Related to Fracture Mechanics,” International Journal for Numerical Method in Engineering, Vol. 20, pp. 2175-2195, 1984.
77. R. Glowinski, M. Vidrascu, and P. Letallec, “Augmented Lagrangian Techniques for Solving Frictionless Contact Problems in Finite Elasticity,” Proc. of the Europe-US Symposium on Finite Element Methods for Nonlinear Problems, pp. 745-58, 1985, Trondheim, Norway.
78. J. C. Simo and R. L. Taylor, “Quasi-Incompressible Finite Elasticity in Principal Stretches. Continuum Basis and Numerical Algorithms,” Computer Methods in Applied Mechanics & Engineering, Vol. 85, pp. 273-310, 1991.
79. J. C. Simo and T. A. Laursen, “An Augmented Lagrangian Treatment of Contact Problems Involving Friction,” Computer & Structures, Vol. 42, pp. 97-116, 1992.
80. H. B. Huntington, “Diffusion in Solids: Recent Developments,” Academic Press, New York, pp. 303-352, 1975.
81. J. R. Black, “Electromigration failure modes in aluminum metallization for semiconductor devices,” Proceedings of the IEEE, Vol. 57, No. 9, pp. 1587-1594, 1969.
82. C. Y. Chang and S. M. Sze, “ULSI Technology,” McGraw-Hill, New York, 1996.
83. S. R. Wilson and C. J. Tracy, “Handbook of Multilevel Metallization for integrated Circuits: Materials, Technology, and Applications,” Noyes, New Jersey, 1993.
84. A. Christou, “Electromigration and Electronic Device Degradation,” John Wiley & Sons, New York, 1994.
85. D. Gupta and P. S. Ho, “Diffusion Phenomena in Thin Films and Microelectronic Materials,” Noyes, New Jersey, 1988.
86. K. N. Tu, J. W. Mayer, and L. C. Feldman, “Electronic Thin Film Science for Electrical Engineers and Materials Scientists,” Macmillan Publishing Company, New York, 1992.
87. K. N. Tu, “Recent advances on electromigration in very-large-scale-integration of interconnects,” Journal of Applied Physics, Vol. 94, No. 4, pp. 5452-5473, 2003.
88. I. A. Blech, “Electromigration in thin aluminum films on titanium nitride,” Journal of Applied Physics, Vol. 47, pp. 1203-1208, 1976.
89. I. A. Blech and C. Herring, “Stress Generation by Electromigration,” Applied Physics Letters, Vol. 29, No. 3, pp. 131-133, 1976.
90. I. Ames, F. M. d’Heurle, and R. Horstman, “Reduction of Electromigration in Aluminum Films by Copper Doping,” IBM Journal of Research and Development, Vol 14, pp. 461-463, 1970.
91. T. M. Shaw, C. K. Hu, K. Y. Lee, and R. Rosenberg, “The microstructural stability of Al(Cu) lines during electromigration,” Applied Physics Letters, Vol. 67, No. 16, pp. 2296-2298, October 1995.
92. J. Proost and K. Maex, “Electromigration-induced drift in damascene and plasma-etched Al(Cu) and Mass transport mechanisms in bamboo interconnects,” Journal of Applied Physics, Vol. 87, No. 1, pp. 99-109, 2000.
93. C. K. Hu, M. B. Small, and P. S. Ho, “Electromigration in Al(Cu) two-level structures: effect of Cu and kinetics of damage formation,” Journal of Applied Physics, Vol. 74, No. 2, pp. 969-978, 1993.
94. C. K. Hu, P. S. Ho, and M. B. Small, “Electromigration in two-level interconnect structures with Al alloy lines and W studs,” Journal of Applied Physics, Vol. 72, No. 1, pp. 291-293, 1992.
95. C. K. Hu, M. B. Small, K. Rodbell, C. Stains, P. Blauner, and P. S. Ho, “Electromigration failure due to interfacial diffusion in fine Al alloy lines,” Applied Physics Letters, Vol. 62, No. 9, pp. 1023-1025, 1993.
96. C. K. Hu, N. J. Mazzeo, and C. Stanis, “Electromigration in Two-Level Bamboo Grain Structure Al(Cu)/W Interconnections,” Materials Chemistry and Physics, Vol. 35, No. 1, pp. 95-98, 1993.
97. C. K. Hu, “Electromigration Failure Mechanisms in Bamboo-Grained Al(Cu) Interconnections,” Thin Solid Films, Vol. 260, No. 1, pp. 124-134, 1995.
98. S. Vaidya, T. T. Sheng, and A. K. Sinha, “Linewidth dependence of electromigration in evaporated Al-0.5%Cu,” Applied Physics Letters, Vol. 36, No. 6, pp.464-466, 1980.
99. A. S. Oates, “Electromigration transport mechanisms in Al thin-film conductors,” Journal of Applied Physics, Vol. 79, No. 1, pp. 163-169, 1996.
100. C. K. Hu, S. Chang, M. B. Small, and J. E. Lewis, “Diffusion barrier studies for Cu,” Proc. of the 3rd International IEEE VLSI Multilevel Interconnection Conference, pp. 181-187, 1986, Santa Clara, USA.
101. P. L. Pai and C. H. Ting, “Copper as the future interconnection materials,” Proc. of the 6th International IEEE VLSI Multilevel Interconnection Conference, pp. 258-264, 1989, Santa Clara, USA.
102. C. K. Hu, M. B. Small, F. Kaufman, and D. J. Pearson, “Copper-Polyimide Wiring Technology for VLSI Circuits,” Proc. of the MRS Symposium on VLSI V, pp. 369-373, 1990, Santa Clara, USA.
103. C. K. Hu and J. M. E. Harper, “Copper Interconnections and Reliability,” Materials Chemistry and Physics, Vol. 52, No. 5, pp. 5-16, 1998.
104. C. K. Hu and B. Luther, “Electromigration in two-level interconnects of Cu and Al alloys,” Materials Chemistry and Physics, Vol. 41, No. 1, pp. 1-7, 1995.
105. J. R. Lloyd and J. J. Clement, “Electromigration in copper conductors,” Thin Solid Films, Vol. 262, pp. 135-141, 1995.
106. E. Liniger, L. Gignac, C. K. Hu, and S. Kaldor, “In situ study of void growth kinetics in electroplated Cu lines,” Journal of Applied Physics, Vol. 92, No. 4, pp. 1803-1810, 2002.
107. C.-K. Hu R. Rosenberg, and K. Y. Lee, “Electromigration path in Cu thin-film lines,” Applied Physics Letters, Vol. 74, No. 20, pp. 2945-2947, 1999.
108. K. L. Lee, C. K. Hu, and K. N. Tu, “In situ scanning electron microscope comparison studies on electromigration of Cu and Cu(Sn) alloys for advanced chip interconnects,” Journal of Applied Physics, Vol. 78, No. 7, pp. 4428-4437, 1995.
109. J. W. Nah, K. W. Paik, J. O. Suh, and K. N. Tu, “Mechanism of electromigration-induced failure in the 97Pb-3Sn and 37Pb-63Sn composite solder joints,” Journal of Applied Physics, Vol. 94, No. 12, pp. 7560-7566, 2003.
110. E. C. C. Yeh, W. J. Choi, K. N. Tu, P. Elenius, and H. Balkan, “Current-crowding-induced electromigration failure in flip chip solder joints,” Applied Physics Letters, Vol. 80, No. 4, pp. 580-582, 2002.
111. K. M. Chen, J. D. Wu, and K, N. Chiang, “Effects of pre-bump probing and bumping processes on eutectic solder bump electromigration,” Microelectronics Reliability, Vol. 46, No. 12, pp. 2104-2111, 2006.
112. J. H. Choi, S. W. Jun, H. J. Won, B. Y. Jung, T. S. Oh, and K,. N. Tu, “Electromigration Reliability of Flip-Chip Bonded Sn-3.5Ag-0.5Cu Solder Bumps on Thick Cu and Thin Ni(V)/Cu Under Bump Metallurgies,” Journal of the Korean Physical Society, Vol. 47, pp. S454-S458, 2005.
113. H. U. Schreiber, “Electromigration threshold in aluminum films,” Solid State Electron, Vol. 28, No. 6, pp. 617-626, 1985.
114. R. G. Filippi, G. A. Biery and R. A. Wachnik, “The electromigration short-length effect in Ti-AlCu-Ti metallization with tungsten studs,” Journal of Applied Physics, Vol. 78, No. 6, pp. 3756-3768, 1995.
115. I. A. Blech and K. L. Tai, “Measurement of stress gradients generated by electromigration,” Applied Physics Letters, Vol. 30, No. 8, pp. 387-389, 1977.
116. P. C. Wang, G. S. Cargill III, I. C. Noyan, and C. K. Hu, “Electromigration-induced stress in aluminum conductor lines measured by X-ray microdiffraction,” Applied Physics Letters, Vol. 72, No. 11, pp. 1296-1298, 1998.
117. P. C. Wang and R. G. Filippi, “Electromigration threshold in copper interconnects,” Applied Physics Letters, Vol. 78, No. 23, pp. 3598-3600, 2001.
118. S. P. Hau-Riege, “Probabilistic immortality of Cu damascene interconnects,” Journal of Applied Physics, Vol. 91, No. 4, pp. 2014-2022, 2002.
119. D. Ney, X. Federspiel, V. Girault, O. Thomas, and P. Gergaud, “Stress-Induced Electromigration Backflow Effect in Copper Interconnects,” IEEE Transactions on Device and Materials Reliability, Vol. 6, No. 2, pp. 175-180, 2006.
120. P. S. Ho, K. D. Lee, S. Yoon, X. Lua, and E. T. Ogawa, “Effect of low k dielectrics on electromigration reliability for Cu interconnects,” Materials Science in Semiconductor Processing, Vol. 7, pp. 157-163, 2004.
121. A. V. Vairagar, S. G. Mhaisalkar, and A. Krishnamoorthy, “Electromigration behavior of dual-damascene Cu interconnects - Structure, width, and length dependences,” Microelectronics Reliability, Vol. 44, pp. 747-754, 2004.
122. A. Roy, C. M. Tan, R. Kumar, and X. T. Chen, “Effect of test condition and stress free temperature on the electromigration failure of Cu dual damascene submicron interconnect line-via test structures,” Microelectronics Reliability, Vol. 45, No. 9-11, pp. 1443-1448, 2005.
123. K. N. Chiang, C. C. Lee, C. C. Lee, and K. M. Chen, “Current crowding-induced electromigration in SnAg3.0Cu0.5 microbumps,” Applied Physics Letters, Vol. 88, No. 7, 072102, 2006.
124. C. C. Lee, C. C. Lee, C. C. Chiu, K. M. Chen, F. Kuo, and K. N. Chiang, “Electromigration Characteristic of SnAg3.0Cu0.5 Flip Chip Interconnection,” Proc. of the 56th Electronic Components and Technology Conference, pp. 1164-1169, 2006, San Diego, USA.
125. K. Weide-Zaage, D. Dalleau, Y. Danto, and H. Fremont, “Void formation in a copper-via-structure depending on the stress free temperature and metallization geometry,” Proc. of the 5th EuroSimE, pp. 367-372, 2004, Brussels, Belgium.
126. K. Weide-Zaage, D. Dalleau, and X. Yu, “Static and dynamic analysis of failure locations and void formation in interconnects due to various migration mechanisms,” Materials Science in Semiconductor Processing, Vol. 6, No.1-3, pp. 85-92, 2003.
127. D. Dalleau and K. Weide-Zaage, “Three-Dimensional Voids Simulation in chip Metallization Structures: a Contribution to Reliability Evaluation,” Microelectronics Reliability, Vol. 41, No. 9, pp. 1625-1630, 2001.
128. D. Dalleau, K. Weide-Zaage, and Y. Danto, “Simulation of time depending void formation in copper, aluminum and tungsten plugged via structures,” Microelectronics Reliability, Vol. 43, No. 9, pp. 1821-1826, 2003.
129. K. Weide-Zaage and V. Hein, “Simulation of Mass Flux Divergence Distributions for an Evaluation of Commercial Test Structures with Tungsten-plugs,” Proc. of the 6th EuroSimE, pp. 254-258, 2005, Berlin, Germany.
130. K. Sasagawa, S. Uno, N. Yamaji, and M. Saka, “Effect of Line-Shape on Threshold Current Density of Electromigration Damage in Bamboo Lines,” Proc. of InterPACK’05, pp. 1147-1152, 2005, San Francisco, USA.
131. K. Sasagawa, M. Hasegawa, M. Saka, and H. Ab□, “Governing Parameter for Electromigration Damage in the Polycrystalline Line with a Passivation Layer,” Journal of Applied Physics, Vol. 91, No. 4, pp.1882-1890, 2002.
132. J. A. Ruud, D. Josell, F. Spaepen, and A. L. Greer, “A new method of tensile testing of thin films,” Journal of Materials Research, Vol. 8, No. 1, pp. 112-117, 1993.
133. L. S. Schadler and I. C. Noyan, “Quantitative measurement of the stress transfer function in nickel/polyimide thin film/copper thin film structures,” Applied Physics Letters, Vol. 66, No. 1, pp. 22-24, 1995.
134. S. P. Baker and W. D. Nix, “Intrinsic stresses in compositionally modulated Au-Ni thin films and the supermodulus effect,” Journal of Materials Research, Vol. 9, No. 12, pp. 3145-3152, 1994.
135. T. P. Weihs, S. Hong, J. C. Bravman, and W. D. Nix, “Testing the Mechanical Properties of Thin Films,” Journal of Materials Research, Vol. 3, No. 5, pp. 931-942, 1988.
136. D. S. Gardner and P. A. Flinn, “Mechanical Stress as a Function of Temperature in Aluminum Films,” IEEE Transactions on Electron Devices, Vol. 35, No. 12, pp. 2160-2169, 1988.
137. D. S. Gardner and P. A. Flinn, “Mechanical stress as a function of temperature for aluminum alloy films,” Journal of Applied Physics, Vol. 67, No. 4, pp. 1831-1844, 1990.
138. P. A. Flinn, D. S. Gardner, and W. D. Nix, “Measurement and Interpretation of Stress in Aluminum-Based Metallization as a Function of Thermal History,” IEEE Transactions on Electron Devices, Vol. ED-34, No. 3, pp. 689-699, 1987.
139. P. A. Flinn, “Measurement and interpretation of stress in copper films as a function of thermal history,” Journal of Materials Research, Vol. 6, No. 7, pp. 1498-1501, 1991.
140. P. R. Besser, S. Brennan, and J. C. Bravman, “An X-ray method for direct determination of the strain state and strain relaxation in micronscale passivated metallization lines during thermal cycling,” Journal of Materials Research, Vol. 9, No. 1, pp. 13-24, 1994.
141. P. A. Flinn and C. Chiang, “X-ray diffraction determination of the effect of various passivations on stress in metal films and patterned lines,” Journal of Applied Physics, Vol. 67, No. 6, pp. 2927-2931, 1990.
142. Q. Ma, S. Chiras, D. R. Clarke, and Z. Suo, “High-resolution determination of the stress in individual interconnect lines and the variation due to electromigration,” Journal of Applied Physics, Vol. 78, No. 3, pp. 1614-1622, 1995.
143. R. S. Hemmert and M. Costa, “Electromigration-induced compressive stresses in encapsulated thin-film conductors,” Proc. of the 29th International Reliability Physics Symposium, pp. 64-69, 1991, Las Vegas, USA.
144. A. B. Horsfall, J. M. M. dos Santos, S. M. Soare, N. G. Wright, A. G. O’Neill, S. J. Bull, A. J. Walton, A. M. Gundlach, and J. T. M. Stevenson, “Direct measurement of residual stress in sub-micron interconnects,” Semiconductor science and technology, Vol. 18, pp. 992-996, 2003.
145. C. J. Wilson, A. B. Horsfall, A. G. O’Neill, N. G. Wright, S. J. Bull, J. G. Terry, J. Tom M. Stevenson, and A. J. Walton, “Direct Measurement of Electromigration-Induced Stress in Interconnect Structures,” IEEE Transactions on Device and Materials Reliability, Vol. 7, No. 2, pp. 356-362, 2007.
146. M. A. Korhonen, P. B□rgesen, K. N. Tu, and C. Y. Li, “Stress evolution due to electromigration in confined metal lines,” Journal of Applied Physics, Vol. 73, No. 8, pp. 3790-3799, 1993.
147. D. Gan, G. Wang, and P. Ho, “Effects of dielectric material and line width on thermal stresses of Cu line structures,” Proc. of the 4th International Interconnect Technology Conference, pp. 271-273, 2002, Colombo, Sri Lanka.
148. S. H. Rhee, Y. Du, and P. Ho, “Characterization of thermal stresses of Cu/low-k submicron interconnect structures,” Proc. of the 3rd International Interconnect Technology Conference, pp. 89-91, 2001, Piscataway, USA.
149. P. R. Besser, E. Zschech, W. Blum, D. Winter, R. Ortega, S. Rose, M. Herrick, M. Gall, S. Thrasher, M. Tiner, B. Baker, G. Braeckelmann, L. Zhao, C. Simpson, C. Capasso, H. Kawasaki, and E. Weitzman, “Microstructural characterization of inlaid copper interconnect lines,” Journal of Electronic Materials, Vol. 30, No. 4, pp. 320-330, 2001.
150. Y. B. Park and I. S. Jeon, “Effects of mechanical stress at no current stressed area on electromigration reliability of multilevel interconnects,” Microelectronic Engineering, Vol. 71, No. 1, pp. 76-89, 2004.
151. C. J. Zhai, H. W. Yao, A. P. Marathe, P. R. Besser, and R. C. Blish, “Simulation and Experiments of Stress Migration for Cu/low-k BEoL,” IEEE Transactions on Device and Materials Reliability, Vol. 4, No. 3, pp. 523-529, 2004.
152. H. Ye, C. Basaran, and D. C. Hopkins, “Numerical Simulation of Stress Evolution During Electromigration in IC Interconnect Lines,” IEEE Transactions on Components and Packaging Technologies, Vol. 26, No. 3, pp. 673-681, 2003.
153. J. Curry, G. Fitzgibbon, Y. Guan, R. Muollo, G. Nelson, and A. Thomas, “New Failure Mechanisms in Sputtered Aluminum-Silicon Films,” Proc. of the 22nd International Reliability Physics Symposium, pp. 6-8, 1984, Las Vegas, USA.
154. H. Okabayashi, “Stress-induced void formation in metallization for integrated circuits,” Material Science and Engineering, Vol. R11, No. 5, pp. 191-241, 1993.
155. T. D. Sullivan, “Stress-induced Voiding in Microelectronic Metallization: Void Growth Models and Refinements,” Annual Review of Materials Science, Vol. 26, pp. 333-364, 1996.
156. T. Turner and K. Wendel, “The Influence of Stress on Aluminum Conductor Life,” Proc. of the 23rd International Reliability Physics Symposium, pp. 142-147, 1985, Orlando USA.
157. S. Domae, H. Masuda, K. Tateiwa, Y. Kato, and M. Fujimoto, “Stress-Induced Voiding in Stacked Tungsten Via Structure,” Proc. of the 36th International Reliability Physics Symposium, pp. 318-323, 1998, Reno, USA.
158. S. Mayumi, T. Umemoto, M. Shishino, H. Nanatsue, S. Ueda, and M. Inoue, “The Effect of Cu Addition to Al-Si Interconnects on Stress Induced Open-Circuit Failures,” Proc. of the 25th International Reliability Physics Symposium, pp. 15-21, 1987, San Diego, USA.
159. A. Tezaki, T. Mineta, and H. Egawa, “Measurement of Three Dimensional Stress and Modeling of Stress Induced Migration failure in Aluminum Interconnects,” Proc. of the 28th International Reliability Physics Symposium, pp. 221-229, 1990, New Orleans, USA.
160. J. W. McPherson and C. F. Dunn, “A model for stress-induced metal notching and voiding in very large-scale-integrated Al-Si(1%) metallization,” Journal of Vacuum Science and Technology B, Vol. 5, No. 5, pp. 1321-1325, 1987.
161. A. F. Bower and L. B. Freund, “Analysis of stress-induced void growth mechanisms in passivated interconnect lines,” Journal of Applied Physics, Vol. 74, No. 6, pp. 3855-3868, 1993.
162. Y. Kawano and T. Ohta, “A New Analysis of Stress Relaxation Phenomena for Stress-Migration Tolerance Estimation,” Proc. of the 33rd International Reliability Physics Symposium, pp. 353-358, 1995, Las Vegas, USA.
163. E. T. Ogawa, J. W. McPherson, J. A. Rosal, K. J. Dickerson, T. C. Chiu, L. Y. Tsung, M. K. Jain, T. D. Bonifield, J. C. Ondrusek, and W. R. McKee, “Stress-Induced Voiding Under Vias Connected To Wide Cu Metal Leads,” Proc. of the 40th International Reliability Physics Symposium, pp. 312-321, 2002, Dallas, USA.
164. M. Abe, N. Furutake, S. Saito, N. Inoue, and Y. Hayashi, “Effects of the Metallurgical Properties of Upper Cu Film on Stress-Induced Voiding (SIV) in Cu Dual-Damascene Interconnects,” Japanese Journal of Applied Physics, Vol. 44, pp. 2294-2302, 2005.
165. M. Kawano, T. Fukase, Y. Yamamoto, T. Ito, S. Yokogawa, H. Tsuda, Y. Kunimune, T. Saitoh, K. Ueno, and M. Sekine, “Stress relaxation in dual-damascene Cu interconnects to suppress stress-induced voiding,” Proc. of the 5th International Interconnect Technology Conference, pp. 210-212, 2003, San Francisco, USA.
166. T. Tonegawa, M. Hiroi, K. Motoyama, K. Fujii, and H. Miyamoto, “Suppression of bimodal stress-induced voiding using high-diffusive dopant from Cu-alloy seed layer,” Proc. of the 5th International Interconnect Technology Conference, pp. 216-218, 2003, San Francisco, USA.
167. K. Y. Y. Doong, R. C. J. Wang, S. C. Lin, L. J. Hung, C. C. Chiu, D. Su, K. Wu, K. L. Young, and Y. K. Peng, “Stress-Induced voiding and its geometry dependency characterization,” Proc. of the 41st International Reliability Physics Symposium, pp. 156-160, 2003, Dallas, USA.
168. C. D. Hartfield, E. T. Ogawa, Y. J. Park, T. C. Chiu, and H. Guo, “Interface Reliability Assessments for Copper/Low-k Products,” IEEE Transactions on Device and Materials Reliability, Vol. 4, No. 2, pp. 129-141, 2004.
169. R. C. J. Wang, C. C. Lee, L. D. Chen, K. Wu, and K. S. Chang-Liao, “A Study of Cu/Low-k Stress-induced Voiding at Via Bottom and Its Microstructure Effect,” Microelectronics Reliability, Vol. 46, No. 9-11, pp. 1673-1678, 2006.
170. H. Tsuchikawa1, Y. Mizushima, T. Nakamura, T. Suzuki1, and H. Nakajima, “Simple Modeling and Characterization of Stress Migration Phenomena in Cu Interconnects,” Japanese Journal of Applied Physics, Vol. 45, No. 2A, pp. 714-719, 2006.
171. Y. P. Kim, D. C. Kwon, H. M. Choi, Y. W. Park, and S. I. Lee, “The effect of residual tensile stress on electromigration lifetime of metal lines passivated by various oxides,” Proc. of the 2nd International Interconnect Technology Conference, pp. 205-207, 2000, Burlingame, USA.
172. K. N. Tu, “Electromigration in stressed thin films,” Physical Review B, Vol. 45, No. 3, pp. 1409-1413, 1992.
173. E. M. Atakov, J. Ling, J. Maziarz, A. Shepela, B. Miner, C. England, W. Harris, and D. Dunnell, “Effect of A1 Alloy and Stacked Film Composition on Linewidth Dependence of Electromigration Lifetime,” Proc. of the 33rd International Reliability Physics Symposium, pp. 342-352, 1995, Las Vegas, USA.
174. D. C. Kwon, Y. J. Wee, Y. H. Park, H. D. Lee, H. K. Kang, and M. Y. Lee, “Underlayer Type Dependence of EM Threshold in AI-CU Interconnect,” Proc. of the 1st International Interconnect Technology Conference, pp. 143-145, 1999, San Francisco, USA.
175. K. W. Lee et al., “Effect of Mechanical Strength and Residual Stress of Dielectric Capping Layer on Electromigration Performance in Cu/Low-k Interconnects,” Proc. of the 50th IEEE International Electron Devices Meeting, pp. 957-960, 2004, Austin, USA.
176. C. S. Hau-Riege and C. V. Thompson, “The effects of microstructural transitions at width transitions on interconnect reliability,” Journal of Applied Physics, Vol. 87, No. 12, pp. 8467-8472, 2000.
177. K. Hoshino, K. Koyania, and Y. Sugano, “Electromigration after Stress-Induced Migration Test in Quarter-Micron Al Interconnects” Proc. of the 32nd International Reliability Physics Symposium, pp. 252-255, 1994, San Jose, USA.
178. A. S. Oates, “Electromigration in Stress-Voided Al Alloy Conductors,” Proc. of the 31st International Reliability Physics Symposium, pp. 297-303, 1993, Atlanta, USA.
179. A. H. Fischer and A. E. Zitzelsberger, “The quantitative assessment of stress-induced voiding in process qualification,” Proc. of the 39th International Reliability Physics Symposium, pp. 334-340, 2001, Orlando, USA.
180. E. M. Atakov, J. J. Clement, and B. Miner, “Two Electromigration Failure Modes in Polycrystalline Aluminum Interconnects,” Proc. of the 32nd International Reliability Physics Symposium, pp. 213-224, 1994, San Jose, USA.
181. S. H. Lee and D. Kwon, “The analysis of thermal stress effect on electromigration failure time in Al alloy thin-film interconnects,” Thin Solid Films, Vol. 341, No. 1-2, pp. 136-139, 1999.
182. T. Kwok, K. K. Chan, H. Chan, and J. Simko, “Thermal stress-induced and electromigration -induced void-open failures in Al and Al-Cu fine lines,” Journal of Vacuum Science and Technology A, Vol. 9, No. 4, pp. 2523-2526, 1991.
183. C. T. Rosenmayer, F. R. Brotzen, J. W. McPherson, and C. F. Dunn, “Effect of stresses on electromigration,” Proc. of the 29th International Reliability Physics Symposium, pp. 52-56, 1991, Las Vegas, USA.
184. F. R. Brotzen, C. T. Rosenmayer, C. F. Dunn, and J. W. McPherson, “Effect of stresses on void nucleation during electromigration,” Proc. of Material Research Society Symposium, Vol. 239, pp. 689-694, Material Research Society, 1992.
185. H. Kahn and C. V. Thompson, “Effect of applied mechanical stress on the electromigration failure times of aluminum interconnects,” Applied Physics Letters, Vol. 59, No. 11, pp. 1308-1310, 1991.
186. W. F. Chen and D. J. Han, “Plasticity for Structural Engineers,” Cau Lih, Taipei, pp. 239-249, 1995.
187. R. D. Cook, D. S. Malkus, and M. E. Plesha, “Concepts and Applications of Finite Element Analysis, 3rd edition,” Wiley, New York, pp. 504-505, 1989.
188. H. D. Solomon, “Low Cycle Fatigue of Sn96 Solder with Reference to Eutectic Solder and a High Pb solder,” ASME Transactions on Journal of Electronic Packaging, Vol. 113, pp. 102-108, 1991.
189. C. Kanchanomai, Y. Miyashita, and Y. Mutoh, “Low-Cycle Fatigue Behavior of Sn-Ag, Sn-Ag-Cu, and Sn-Ag-Cu-Bi Lead-Free Solders,” Journal of Electronic Materials, Vol. 31, No. 5, pp. 456-465, 2002.
190. K. O. Lee, J. Yu, T. S. Park, and S. B. Lee, “Low-Cycle Fatigue Characteristics of Sn-Based Solder Joints,” Journal of Electronic Materials, Vol. 33, No. 4, pp. 249-257, 2004.
191. C. Andersson, Z. Lai, J. Liu, H. Jiang, and Y. Yu, “Comparison of isothermal mechanical fatigue properties of lead-free solder joints and bulk solders,” Materials Science and Engineering A, Vol. 394, pp. 20-27, 2005.
192. S. S. Manson, “Behavior of Materials Under Conditions of Thermal Stress,” NACA TN-2933, National Advisory Committee for Aeronautics, Cleveland, 1954.
193. L. F. Coffin, “Design Aspects of High Temperature Fatigue with Particular Reference to Thermal Stress,” ASME Transaction, Vol. 78, pp. 527-532, 1955.
194. J. Morrow, J. F. Martin, and N. E. Dowling, “Local Stress-Strain Approach to Cumulative Fatigue Damage Analysis,” Final Report, T & A. M. Report No. 379, Department of Theoretical and Applied Mechanics, University of Illinois, Urbana, 1974.
195. W. Engelmaier, “A New Ductility and Flexural Fatigue Test Method for Copper Foil and Flexible Printed Wiring,” IPC-TP-204, Institute for Interconnecting and Packaging Electronic Circuits, Evanston, USA, 1978.
196. W. Engelmaier, “Flexural Fatigue and Ductility, Foil,” IPC-TM-650, Institute for Interconnecting and Packaging Electronic Circuits, Lincolnwood, USA, 1980.
197. W. Engelmaier and A. Wagner, “Fatigue Behaviour and Ductility Determination for Roller Annealed Copper Foil and Flex Circuits on Kapton,” Circuit world, Vol. 14, No. 2, pp. 30-38, 1988.
198. W. Engelmaier, “Results of the IPC copper foil ductility round-robin study,” Testing of Metallic and Inorganic Coatings, ASTM STP 947, Philadelphia, USA, pp. 66-95, 1987.
199. R. Iannuzzelli, “Predicting Plated-Through-Hole Reliability in High Temperature Manufacturing Processes,” Proc. of the 41st Electronic Components and Technology Conference, pp. 410-421, 1991, Atlanta, USA.
200. R. V. Pucha, G. Ramakrishna, S. Mahalingam, and S. K. Sitaraman, “Modeling spatial strain gradient effects in thermo-mechanical fatigue of copper microstructures,” International Journal of Fatigue, Vol. 26, No. 9, pp. 947-957, 2004.
201. Z. H. Zhong, “Finite Element Procedures for Contact-Impact Problems,” Oxford University Press, New York, 1993.
202. T. Belytschko, W. K. Liu, and B. Moran, “Nonlinear Finite Elements for Continua and Structures, 1st edition,” John Wiley & Sons, New York, 2000.
203. R. Glowinski and P. L. Tallec, “Augmented Lagrangian and Operator-Splitting Methods in Nonlinear Mechanics,” SIAM Studies in Applied Mathematics, Philadelphia, 1989.
204. A. Kazama, T. Satoh, Y. Yamaguchi, I. Anjoh, and A. Nishimura, “Development of Low-cost and Highly Reliable Wafer Process Package,” Proc. of the 51st Electronic Components and Technology Conference, pp. 40-46, 2001, Florida, USA.
205. X. Fan, M. Pei, and P. K. Bhatti1, “Effect of Finite Element Modeling Techniques on Solder Joint Fatigue Life Prediction,” Proc. of the 56th Electronic Components and Technology Conference, pp. 972-980, 2006, San Diego, USA.
206. V. Fiori and S. Orain, “A Multi Scale Methodology to Evaluate Wire Bond Pad Architecture,” Proc. of the 6th EuroSimE, pp. 648-655, 2005, Berlin, Germany.
207. K. C. Chang and K. N. Chiang, “Growth analysis of interfacial delamination in a plastic ball grid array package during solder reflow using the global-local finite element model,” Journal of Strain Analysis, Vol. 41, No. 1, pp. 19-30, 2006.
208. C. C. Lee, T. L. Chou, C. C. Chiu, C. C. Hsia, and K. N. Chiang, “Cracking energy estimation of ultra low-k package using novel prediction approach combined with global-local modeling technique,” Microelectronic Engineering, Vol. 85, pp. 2079-2084, 2008.
209. C. Kittel, “Introduction to Solid State Physics,” John Wiley &Sons, New York, 1996.
210. V. B. Fiks, “On the Mechanism of the Mobility of Ions in Metals,” Soviet Physics, Solid State, Vol. 1, No. 1, pp. 14-28, 1959.
211. H. B. Huntington and A. R. Grone, “Current-Induced Marker Motion in Gold Wires,” Journal of Physics and Chemistry of Solids, Vol. 20, No. 1-2, pp. 76-87, 1961.
212. R. S. Sorbello, “Theory of the Direct Force in Electromigration,” Physical Review B, Vol. 31, No. 2, pp. 798-804, 1985.
213. R. P. Gupta, “Theory of Electromigration in Noble and Transition Metals,” Physical Review B, Vol. 25, No. 8, pp. 5188-5196, 1982.
214. J. D. Plummer, M. D. Deal, and P. B. Griffin, “Silicon VLSI Technology: Fundamentals, Practice, and Modeling,” Prentice Hall, New York, 2000.
215. F. Fantini, J. R. Lloyd, I. D. Munari, and A. Scorzoni, “Electromigration Testing of Integrated Circuit Interconnections,” Microelectronic Engineering, Vol. 40, No. 3, pp. 207-221, 1998.
216. C. S. Hau-Riege, “Current Challenges in Cu Electromigration Reliability,” Tutorial Note of the International Integrated Reliability Workshop, pp. 232-232, 2006, South Lake, USA.
217. C. T. Su, “The Robust Design of Product,” Chinese Society for Quality, Taipei, pp. 9-36, 2000.
218. L. G. Johnson, “The Median Ranks of Sample Values in their Population with an Application to Certain Fatigue Studies,” Industrial Mathematics, Vol. 2, pp. 1-9, 1951.
219. S. M. Chang, C. Y. Cheng, L. C. Shen, K. N. Chiang, Y. J. Hwang, Y. F. Chen, C. T. Ko, and K. C. Chen, “A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication,” IEEE Transactions on Advanced Packaging, Vol. 30, No. 3, pp. 377-383, 2007.
220. M. C. Yew, C. C. Chiu, S. M. Chang, and K. N. Chiang, “A Novel Crack and Delamination Protection Mechanism for a WLCSP Using Soft Joint Technology,” Soldering & Surface Mount Technology, Vol. 18, No. 3, pp. 3-13, 2006.
221. M. C. Yew, S. M. Chang, and K. N. Chiang, “Reliability Analysis of a New Soft Joint Protection Technology Using in WLCSP,” Proc. of the 1st International Microsystems, Packaging, Assembly Conference, pp. 151-154, 2006, Taipei, Taiwan.
222. M. C. Yew, C. Yuan, C. N. Han, C. S. Huang, W. K. Yang, and K. N. Chiang, “Factorial Analysis of Chip-on-Metal WLCSP Technology with Fan-Out Capability,” Proc. of the 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp. 223-228, 2006, Singapore.
223. H. P. Wei, M. C. Yew, W. K. Yang, and K. N. Chiang, “Reliability Analysis of a Package-on-Package Structure Using Novel WLCSP Technology with Fan-Out Capability,” Proc. of the 8th International Conference on Electronics Materials and Packaging, pp. 164-170, 2006, Hong Kong.
224. M. C. Yew, H. P. Wei, C. S. Huang, D. C. Hu, W. K. Yang, and K. N. Chiang, “A Study of Failure Mechanism and Reliability Assessment for the Panel Level Package (PLP) Technology,” Proc. of the 8th EuroSimE, pp. 475-482, 2007, London, England.
225. H. P. Wei, M. C. Yew, and K. N. Chiang, “FAILURE MODE AND THERMAL PERFORMANCE ANALYSIS OF STACKED PANEL LEVEL PACKAGE (PLP),” Proc. of the InterPACK’07, pp. 693-701, 2007, Vancouver, Canada.
226. M. C. Yew and K. N. Chiang, “A Study of Material Effects for the Panel Level Package (PLP) Technology,” Proc. of the 2nd International Microsystems, Packaging, Assembly and Circuits Technology conference, pp. 98-101, 2007, Taipei, Taiwan.
227. M. C. Yew, C. Y. Chou, and K. N. Chiang, “Reliability Assessment for Solders with a Stress Buffer Layer using Ball Shear Strength Test and Board-level Finite Element Analysis,” Microelectronics Reliability, Vol. 47, No. 9-11, pp. 1658-1662, 2007.
228. M. C. Yew, C. J. Wu, C. S. Huang, M. Tsai, D. C. Hu, W. K. Yang, and K. N. Chiang, “Trace Line Failure Analysis and Characterization of the Panel Base Package (PBPTM) Technology with Fan-Out Capability,” Proc. of the 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, pp. 862-869, 2008, Florida, USA.
229. M. C. Yew, C. F. Yu, M. Tsai, D. C. Hu, W. K. Yang, and K. N. Chiang, “A Study of Thermal Performance for the Panel Base Package (PBPTM) Technology,” Proc. of the International Conference on Electronic Packaging Technology and Symposium on High Density Packaging, 2008, Shanghai, China.
230. H. P. Wei, M. C. Yew, C. J. Wu, and K. N. Chiang, “Reliability and Thermal Assessment of Stacked Chip-on-Metal Panel Based Package (PBPTM) with Fan-Out Capability,” Proc. of the 2nd Electronics Systems-Integration Technology Conference, pp. 327-332, 2008, Greenwich, UK.
231. M. C. Yew, C. F. Yu, M. Tsai, D. C. Hu, W. K. Yang, and K. N. Chiang, “Reliability Analysis of the Panel Base Package (PBPTM) Technology with Enhanced Cover Layer,” Proc. of the 3rd International Microsystems, Packaging, Assembly and Circuits Technology Conference and the 10th International Conference on Electronics Materials and Packaging, pp. 384-387, 2008, Taipei, Taiwan.
232. L. L. Mercado, C. Goldberg, S. M. Kuo, T. Y. Lee, and S. K. Pozder, “Analysis of Flip-Chip Packaging Challenges on Copper/Low-k Interconnects,” IEEE Transactions on Device and Materials Reliability, Vol. 3, No. 4, pp. 111-118, 2003.
233. M. R. Miller and P. S. Ho, “Interfacial Adhesion Study for Copper/SiLK Interconnects in Flip-chip Packages,” Proc. of the 51st Electronic Components and Technology Conference, pp. 965-970, 2001, Orlando, USA.
234. H. A. Schafft, T. C. Staton, J. mandel, and J. D. Shott, “Reproducibility of Electromigration Measurements,” IEEE Transactions on Electron Devices, Vol. ED-34, No. 3, pp. 673-681, 1987.
235. D. Degryse, B. Vandevelde, and E. Beyne, “Mechanical FEM Simulation of Bonding Process on Cu Lowk Wafers,” IEEE Transactions on Components and Packaging Technology, Vol. 27, No. 4, pp. 643-650, 2004.
236. J. K. Lin, A. D. Silva, D. Frear, Y. Guo, S. Hayes, J. W. Jang, L. Li, D. Mitchell, B. Yeung, and B. Zhang, “Characterization of Lead-Free Solders and Under Bump Metallurgies for Flip-Chip Package,” IEEE Transactions on Electronic Packaging Manufacturing, Vol. 25, No. 3, pp. 300-307, 2002.
237. J. H. L. Pang, B. S. Xiong, and F. X. Che, “Modeling Stress Strain Curves For Lead-Free 95.5Sn-3.8Ag-0.7Cu Solder”, Proc. of the 5th EuroSimE, pp. 449-453, 2004, Brussels, Belgium.
238. J. G. Kaufman, “Properties of Aluminum Alloys: Tensile, Creep, and Fatigue Data at High and Low Temperatures,” ASM International, Washington, 1999.
239. K. Y. Lee, C. K. Hu, T. Shaw, and T. S. Kuan, “Fabrication of microstructures for studies of electromigration in sub-0.25 μm metal interconnections,” Journal of Vacuum Science and Technology B, Vol. 13, No. 6, pp. 2869-2874, 1995.
240. J. R. Lloyd, “Black’s law revisited-Nucleation and growth in electromigration failure,” Microelectronics Reliability, Vol. 47, No. 9-11, pp. 1468-1472, 2007.
241. A. S. Oates, “Current density dependence of electromigration failure of submicron width, multilayer Al alloy conductors,” Applied Physics Letters, Vol. 66, No. 12, pp. 1475-1477, 1995.
242. X. Federspiel, D. Ney, and V. Girault, “DETERMINATION OF THE ACCELERATION FACTOR BETWEEN WAFER LEVEL AND PACKAGE LEVEL ELECTROMIGRATION TEST,” Proc. of the 43rd International Reliability Physics Symposium, pp. 658-659, 2005, San Jose, USA.
243. J. R. Lloyd, “Electromigration in integrated circuit conductors,” Journal of Physics D: Applied Physics, Vol. 32, No. 17, pp. R109-R118, 1999.