在此篇論文中，提出了一個符合IEEE 802.15.4標準的基頻收發機，可適用於低速無線個人區域網路(LR-WPAN)的通訊系統，符合低功率消耗與低成本的需求。同時依照標準的設計流程，從系統規格與相關研究的研讀，功能性的模擬，系統架構的設計，到實際電路的設計與晶片的實做。
為了在基頻的部分估計並補償載波頻率及相位上的誤差，接收機採用的是全數位式的相位同步(phase synchronization)架構。因本系統規格所訂定的載波頻率漂移(carrier frequency offset)很大，這篇論文採用了一現有的演算法來進行封包偵測(packet detection)與邊界偵測(boundary detection)，同時估計載波頻率的漂移量。另外為了確保接收機在接收到較長的封包時依然能夠維持原有的效能，這篇論文也提出一個新的決定-回授(decision-feedback)演算法來追蹤殘餘的相位誤差。
這篇論文提出的基頻接收機可提供比IEEE 802.15.4標準所規定更好的系統效能。在訊號雜訊比(SNR)小於5 dB的時候，就可達到1%的封包錯誤率(PER)。
在電路的設計上，為達到低功率的消耗，使用了gated-clock的電路控制技巧。另外在維持系統正常的效能下，多使用簡單的硬體架構，而每塊功能模組間也盡量做到基本電路元件的共用，以節省面積。
本基頻收發機的晶片遵照標準單元(cell-based)設計流程來完成設計，並透過國家晶片系統設計中心(CIC)，使用台積電0.18 um的製程來製造。整顆晶片的面積約為1.63 mm×1.63 mm，而晶片工作在接收模式的時候，其消耗功率約為4.7 mW.

In this thesis, standard specification study, functional simulation, architecture design, and circuit design along with chip implementation of an IEEE 802.15.4 baseband transceiver for low-rate wireless personal area network (LR-WPAN) with full digital synchronization is presented.

In order to estimate and compensate carrier phase error at baseband, the receiver adopts full digital solution for carrier phase synchronization.
An existing packet detection algorithm for spread spectrum communication systems is used for estimating quite large carrier frequency offset.
A new decision-feedback algorithm to track residue phase error for long packet length is also proposed in this thesis.

The proposed receiver achieves system performance (PER = 0.01) at SNR less than 5 dB. It provides better performance than the standard required.

The baseband processor was implemented in simple hardware architecture and designed with low power techniques.
Gated-clock is used for time scheduling to save power consumption.

The transceiver chip is fabricated with TSMC 0.18 um 1P6M CMOS technology.
The area is 1.633 mm X 1.633 mm, and the power consumption is about 4.7 mW at receiver mode.

1 Introduction 1
1.1 Wireless Personal Area Networks 1
1.2 Motivation of the Thesis 3
1.3 Organization of the Thesis 4
2 System Descriptions 7
2.1 IEEE Standard 802.15.4 7
2.2 System Specification 11
2.2.1 General Descriptions 11
2.2.2 Packet Format 12
2.2.3 PHY Specification 12
3 Architecture Design 17
3.1 Transmitter 17
3.2 Receiver 19
3.2.1 Packet Detection 22
3.2.2 De-spreading 26
3.2.3 Phase Synchronization 26
4 Functional Simulation 37
4.1 Baseband Channel Impairments 37
4.1.1 Carrier Frequency Offset 37
4.1.2 AWGN 39
4.1.3 Sampling Frequency Offset 39
4.2 Floating-point Simulation 40
4.2.1 System Performance Simulation 43
5 Circuit Design 45
5.1 Word-length Simulation 45
5.2 Transmitter 51
5.3 Receiver 54
5.3.1 Packet Detection 54
5.3.2 Phase Synchronization 60
5.3.3 De-spreading and Data Recovery 66
5.4 Analysis 69
6 Implementation and Measurement 71
6.1 ASIC Design Flow 71
6.2 Chip Implementation 72
6.3 Measurement Plan 82
7 Discussions and Conclusions 83
7.1 Future Works 83
7.2 Conclusions 85

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