無庸置疑地，在大型積體電路設計上，金屬互連的問題目前備受關注而無法被忽視。系統單晶片趨勢已蔚為潮流，而為了增加每單位面積電晶體的數目、減少漏電流或者達到省電的種種目的必須採用奈米製程來滿足該需求。然而許多新問題也同時接踵而來。其中之一為製程變動。不光是針對金屬線製程，製程變動的問題是整個半導體產業的重大挑戰。所以是否能準確估計金屬線的效能，關鍵仍取決於金屬線變動的分析。唯有靠對於製程變動的正確評估加上於製程上的不斷改進才能提高產品量產成功的機率。
在本論文之中，我們設計了一個非破壞性逆向推導分析流程來模擬目前銅製程金屬互連的製程變動情形，不僅可以提供快速分析測試結構，並且可為金屬互連量產可行性分析來萃取電性並整合統計及邊緣模擬。藉建立出的模型，我們可以利用量測出的資料與模型內資料比對來推測目前製程量產能力是否達到預期目標，方便分析人員在成功量產或者再次檢視這些製程中遇上問題兩者間作取捨。我們並且提供敏感性測試來協助分析人員在模擬的過程中掌握具關鍵性之因素、去除一些不感興趣或者影響程度微小的參數以方便分析上的觀察。此分析可以幫助晶圓廠向更高製程量產的發展邁進。結論以及如何利用測試晶片的資料來對於目前CMOS製程分析的方法在內文中會作更詳細的介紹。

Undoubtedly interconnect problems in VLSI designs deserve more attention and can no longer be neglected. In order to catch up with trend of System-on-Chip, sub-90nm process technology is introduced for increasing transitor numbers on the chip, off current reduction or low power requirement but also bring some new problems. One of them is process variation. Process variation is an overall challenge below 100 nm, and not just for interconnects. Therefore, analysis with these interconnect variations is the basis of accurate estimation of interconnect performance. Only by well assessment on process variation and continuous reformation on process technology that could improve the chance of successful design.
In this paper, we present a non-destructive inverse modeling copper interconnect process flow which not only provide fast analysis on test structure and provide electrical characterization extraction but also integrate statistical and corner modeling method for metal interconnect manufacturability analysis. Based on our model, we could use silicon data form foundry to diagnose current manufacturing capability and to help analysts making decision between successful fabrication or review problems during process. We also provide sensitivity test helping analysts locate critical factors or eliminate the uninterested factors. This analysis could give assistance for foundry manufacturability and look forward to advanced technology. Conclusions and analysis methods of CMOS process problem diagnosis using the data obtained from test chip are summarized.

中文摘要 i
Abstract ii
特別誌謝 iii
ContentsList of Figures iv
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
Chapter 2 Previous Work 5
2.1 Test structure and test chip 5
2.2 Test structure Generator 7
2.3 Neumann Boundary 8
2.4 Comb-meander 10
2.5 SIPPs 11
2.6 Chemical Mechanical Polishing (CMP) 13
2.7 Monte-Calro Simulation 14
Chapter 3 Proposed Method 15
3.1 Test Chip Project Introduction 15
3.2 Test chip Design and Specification 17
3.3 Test structure Design 18
3.4 Field Solver 21
3.5 Simulation flow 22
3.6 Simulation Methodology 23
3.7 Silicon Measurement 29
3.8 Statistical Analysis 31
Chapter 4 Experiment Result 35
4.1 Analysis system description 35
4.2 Silicon Correlation 35
4.3 Sensitivity Analysis 38
4.4 Corner Model set-up 39
Chapter 5 Conclusion and Future Work 43
Reference: 44
Appendix A: Measure steps for test chip 45
Appendix B: Sensitivity Analysis list of TL#117 DUT 8 48
Appendix C: Raphael input file content 49
Appendix D: VBA program code 58
Appendix E: Corner Model Content for DUT8 64

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