本篇論文提出一新穎以梯形閘極氧化層結構的反熔絲記憶元件(Step Gate Oxide Anti-Fuse, SGAF)，此記憶元件可內嵌於一般標準邏輯製程製作之晶片。利用光罩定義在同一閘極上形成厚薄氧化層而成梯形狀，並使用硬崩潰作為單次寫入型之機制，利用淺溝渠(Shallow Trench Isolation)可以避免未寫入記憶元受到貫穿電壓影響，隔離元件之間漏電流干擾。藉特殊元件佈局技巧及薄氧化層比例設計，可以增大電場效應，提升寫入資料速度。SGAF 記憶元件在高電壓寫入時低於4V，可避免大部份非揮發性記憶元件使用的高電壓，所造成的高功率損耗的缺失。元件陣列則採用NOR 型式陣列，並加入字元線選擇電晶體(select transistor)以降低超薄閘極漏電流干擾寫入及讀取情況，提高記憶元件可靠度。
此新穎之梯形閘極反熔絲SGAF 記憶元件驗證於90nm 和65nm 標準邏輯製程，經晶片量測結果顯示，1Kbits 陣列之記憶元件電流分佈，提供足夠的讀取電流差距，達成資料的存取。

In this study, a novel logic One-Time-Programmable (OTP) cell using Step Gate Oxide of Anti-Fuse (SGAF) with fast programming was demonstrated by nano-meter CMOS logic processes for advance logic NVM’s applications. The silicon data has proven that this cell can be adapted in both 90nm & 65nm technology nodes. The SGAF cell features complete compatibility to logic process without any
additional change in process or mask layers. Gate oxide rupture is used as programming mechanism for the SGAF memory cell. The unique design in this cell is creating a oxide thickness difference in this step gate oxide formation. This cell can be programmed under 4V within 10us, while this low programming voltage can greatly
reduce the power consumption as well as complexity in the peripheral circuits.
As the breakdown of gate oxide is used as the programming method in SGAF array memory cell, this device is expected to scale better in advance technologies.

摘要.......................................................I
Abstract................................................. II
致謝.................................................... III
章節目錄................................................. IV
附圖目錄................................................. VI
附表目錄.................................................. X
第一章 緒論............................................... 1
1.1 記憶體介紹及應用...................................... 1
1.2 研究動機.............................................. 2
1.3 論文大綱.............................................. 2
第二章 相關技術及操作原理回顧............................. 5
2.1 一次性寫入型記憶體之回顧.............................. 5
2.2 歸納一次性寫入型記憶體之操作機制...................... 8
2.3 閘極氧化層穿隧電流與崩潰機制之理論模型................ 8
2.4 總結................................................. 12
第三章 梯形閘極氧化層記憶元件(SGAF)製程與操作機制........ 23
3.1 元件製程與結構....................................... 23
3.2 操作原理與干擾問題................................... 24
3.3 元件寫入及讀取模擬分析............................... 26
3.4 總結................................................. 29
第四章 梯形閘極氧化層記憶體元件電性分析.................. 46
4.1 量測系統設備介紹..................................... 46
4.2 元件結構暨閘極氧化層厚度估測......................... 46
4.3 寫入點於氧化層崩潰後之特性........................... 47
4.4 氧化層崩潰特性....................................... 48
4.5 寫入條件的選取....................................... 48
4.6 讀取條件的最佳化..................................... 49
4.7 元件可靠度分析....................................... 49
4.8 總結................................................. 52
第五章 65nm SGAF 記憶體陣列量測結果及微縮影下特性分析.... 68
5.1 65nm 製程下記憶陣列bit cell 電流之分佈............... 68
5.2 製程演進下的特性的改善............................... 70
第六章 結論.............................................. 78
參考文獻................................................. 80

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