本篇論文中，我們利用不同的浮動閘極材料來改善元件特性的想法，提出P型浮動閘極N通道的分離閘快閃式記憶體 (Split Gate Flash Memory)，將浮動閘極之摻雜由N型改為P型，與傳統的N型浮動閘極元件相比較，P型浮動閘極元件擁有較低的寫入偏壓、較快的寫入/抹除 (Program/Erase) 速度與可靠性，較大的操作區間 (Operation Window)、以及較佳的耐久度 (Endurance)。本論文深入探討P摻雜浮動閘極分離閘快閃式記憶體可靠性問題，其中包含：操作耐久性 (Endurance)，抗擾動能力 (Disturbance) 及資料保存能力 (Data Retention) 等特性，並成功的達成了在高可靠度分離閘快閃式記憶體的應用。

摘要 I
Abstract II
目錄 III
附圖目錄 V
附表目錄 VIII
第一章 緒論 1
1.1快閃記憶體介紹 1
1.2 論文大綱 3
第二章 回顧與發展 7
2.1分離閘結構快閃記憶體的發展過程 7
2.1.1 Masuoka等人提出之快閃記憶體元件結構介紹 8
2.1.2 SIEPROM元件結構介紹 9
2.1.3 SISOS元件結構介紹 10
2.1.4 HIMOS元件結構介紹 11
2.1.5 SPIN元件結構介紹 12
2.1.6 Kianian等人提出之分離閘快閃記憶體結構介紹 14
2.2 P型硼摻雜之浮動閘級應用於N通道記憶體之相關論文回顧 15
第三章分離閘快閃記憶體相關技術回顧與可靠性問題 26
3.1 P型浮動閘極的N通道分離閘快閃記憶體之相關論文回顧 26
3.2 記憶體陣列可靠性問題 27
3.2.1寫入/抹除循環耐久度問題 28
3.2.2資料的保存能力 28
3.2.3穿透氧化層衰退的問題 28
3.2.4資料寫入與讀取干擾 29
3.3 分離閘快閃記憶體的可靠性問題 30
3.3.1分離閘快閃記憶體資料寫入干擾問題 30
3.3.2分離閘快閃記憶體字元線寫入干擾問題 30
3.3.3分離閘快閃記憶體位元線寫入干擾問題 31
3.3.4分離閘快閃記憶體對角線寫入干擾問題 31
3.3.5分離閘快閃記憶體資料的保存能力 32
3.3.6分離閘快閃記憶體的讀出干擾問題 33
第四章 可靠度問題與量測特性分析與實驗結果討論 50
4.1 量測環境介紹與建立 50
4.2 受測元件元件結構與操作機制 50
4.2.1 元件的寫入機制 51
4.2.2 元件的抹除機制 51
4.3.3 元件的讀取機制 51
4.3 P與N型懸浮閘N通道分離閘資料寫入效率比較 52
4.4資料寫入效率統一化 52
4.5 P型與N型懸浮閘N通道分離閘抹除效率分析 53
4.6 元件耐久度測試分析與比較 53
4.6.1元件耐久度在高溫以及低溫之測試分析與比較 54
4.7記憶體陣列寫入干擾免疫能力測試分析與比較 55
4.7.1字元線寫入干擾抵抗能力測試分析 55
4.7.2位元線寫入干擾抵抗能力測試分析 55
4.7.3對角線寫入干擾抵抗能力測試分析 56
4.8 資料保存能力測試分析與比較 56
第五章 結論 78
參考文獻 79

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