本研究由界面強度模擬的觀點，探討三維晶片堆疊封裝之完整可靠度分析，以及四點彎折脫層試驗之改良。在可靠度分析中，除了典型的錫球壽命與晶片裂片分析，並引進破裂力學進行銅凸塊間裂縫分析，以及討論銅矽穿孔與銅凸塊結構之壽命。此外，本研究採用改良型虛擬裂縫閉合法(Modified Virtual Crack Closure Technique, MVCCT)與有限單元法(Finite Element Method, FEM)之破裂分析，應用於計算四點彎折脫層試驗之界面脫層行為，並提出修正試片尺寸與部份接合效應之方法。對於四點彎折試驗分析，本研究提出應用於有限單元模型之外力固定邊界條件設定，並加以驗證。此外，試片尺寸效應之修正亦藉由模擬預估與實驗驗證來進行推導；而為達到增加極限界面能量釋放率之量測範圍，本研究提出之部份接合效應亦被證實。基於四點彎折脫層試驗之解析解，本研究推導用於修正試片尺寸效應與部份接合效應之數學模型。
根據在四點彎折試驗分析中對於MVCCT之應用與驗證，本研究將其進一步應用於三維封裝結構之破裂力學分析，使用之測試載具主要由銅導通孔、銅凸塊與ABF層壓物結構所構成。針對由真實三維封裝結構中觀察得到存在於兩連接銅凸塊間的孔洞脫層結構，利用前述方法可加以評估於封裝層級該孔洞脫層擴張的可能性。藉由以模擬得到之界面能量釋放率數值，與文獻所記載之極限值交互比較，可驗證該脫層結構不會發生擴張；相同的分析方法亦應用於層板級之三維封裝結構中，並得到與封裝層級分析相同之結果。此外，本研究提出三種根據測試載具為基礎所設計之三維封裝結構，以探討三維封裝結構於實際量產之可行性，包含錫球壽命、銅導通孔與凸塊壽命、以及晶片裂片分析被同時應用於模擬分析當中。結果顯示應用了技術成熟之打線(Wire Bonding)方法與塑膠球陣列封(Plastic Ball Grid Array, PBGA)裝技術之設計，展現出較佳的綜合可靠度壽命。

From the viewpoint of interfacial strength simulation, an overall reliability analysis of three-dimensional (3D) chip stacking package and the modification of the four-point bending (4PB) delamination test were investigated in this research. In the reliability analysis, aside from typical solder joint life prediction and die-crack analysis, fracture mechanics was introduced for crack examination between copper bumps, as well as copper through silicon via (TSV) and bump life prediction. Moreover, fracture analyses based on modified virtual crack closure technique (MVCCT) and finite element method (FEM) were carried out to evaluate the delamination behavior in the 4PB delamination test, and the modification for specimen size and partially-adhesive effects were proposed. For the 4PB delamination test analysis, the controlled-force loading condition for FEM models was proposed and validated. Besides, the modification for the size effect was derived through simulation predictions and experimental validation. Moreover, to broaden the critical energy release rate (Gc) measuring range when using the same substrate, the concept of partially-adhesive sandwich specimen was developed and validated. The modified equations based on the analytical solution for 4PB delamination tests were derived as well.
Based on the application and validation of MVCCT in the 4PB test analysis, the former was further utilized in the fracture analysis of the 3D package. The test vehicle was mainly composed of copper TSV and bumps, and the ABF (Ajinomoto Built-up Film) lamination structure was designated. According to the vacancy observed in an actual package structure, the embedded delamination between two connecting copper bumps was evaluated to investigate the possibility of delamination expansion for the 3D package at the package level. By validating the simulation G value with the Gc value reported in literature, the delamination expansion should not happen. Moreover, the simulation procedure was performed to predict fracture behavior for the 3D package at the board level, and the results show the same conclusion as that for the package level case. In addition, three kinds of 3D package designs based on the test vehicle were developed to investigate the feasibility of mass production. In this research, several reliability issues including solder joint life, copper TSV and bump life, and die-crack were evaluated through FEM analysis for comparison between each case. The results reveal that the proposed 3D chip stacking package combined with well-developed wire-bonding and plastic ball grid array (PBGA) packaging technology yielded a relatively better performance reliability.

Acknowledgement I
Abstract III
Abstract (Chinese) V
Content VII
Tables IX
Figures X


CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Research Goals 2
1.3 Literature 4
1.3.1 3D Chip-Stacking Electronic Packaging and its Reliability Analysis 4
1.3.2 Solder Joint Reliability Prediction 9
1.3.3 The 4PB Test 12
1.3.4 The Energy Release Rate Measurement of the Patterned Interface 16
1.3.5 Numerical Methods for Fracture Mechanics Based on Finite Element Method 19
CHAPTER 2 THEORY 21
2.1 Reliability Analysis of Microelectronic Packaging 21
2.1.1 An Overview of Fatigue Life 22
2.1.2 Copper Via Thermal Fatigue Life Prediction 25
2.1.3 Solder Joint Thermal Fatigue Life Prediction 27
2.2 Fundamental of the Fracture Mechanics for Engineering Design 28
2.3 The Modified Virtual Crack Closure Technique (MVCCT) 33
2.4 4PB Delamination Test 51
CHAPTER 3 APPLICATION OF INTERFACIAL STRENGTH SIMULATION IN 4PB DELAMINATION TEST 55
3.1 MVCCT Application in Finite Element Analysis 55
3.2 Validation of Loading Condition in MVCCT Application 61
3.3 MVCCT Application in Size Effect Investigation of Sandwich Specimens. 64
3.4 MVCCT Application in Partially-Adhesive Sandwich Specimens 68
CHAPTER 4 EXPERIMENTAL INVESTIGATION AND MODIFICATION OF 4PB DELAMINATION TEST 72
4.1 Introduction to Specimens for 4PB Test 72
4.2 Introduction to the 4PB Delamination Test 78
4.3 Experimental Results 81
4.3.1 Investigation of Size Effect 81
4.3.2 Investigation of Partially-adhesive Effect 84
4.4 Modification of the Analytical Solution for the 4PB Delamination Test 88
4.4.1 Modified Equation for Size Effect 89
4.4.2 Modified Equation for Partially-adhesive Effect 92
CHAPTER 5 APPLICATION OF INTERFACIAL STRENGTH SIMULATION IN 3D CHIP STACKING ELECTRONIC PACKAGE 95
5.1 Introduction to 3D Chip Stacking Package Model 95
5.2 MVCCT Application in Package-Level 3D Chip Stacking Package 102
5.2.1 Mesh Density Effect Discussion 102
5.2.2 Discussion on Delamination Size Effect 106
5.2.3 Experimental Validation 107
5.3 MVCCT Application in Board-Level 3D Chip Stacking Package 107
CHAPTER 6 RELIABILITY ANALYSIS AND DESIGN OF 3D CHIP STACKING ELECTRONIC PACKAGE 110
6.1 Design of Board-Level 3D Chip Stacking Package Model 110
6.2 Reliability Analysis 113
CHAPTER 7 CONCLUSION AND RECOMMENDATION 119
7.1 Conclusion 119
7.2 Recommendation for Future Works 121
REFERENCE 123

[1] R. R. Tummala, "SOP: What is it and why? A new micro system-integration technology paradigm-Moore's law for system integration of miniaturized convergent systems of the next decade," IEEE Transactions on Advanced Packaging, vol. 27, pp. 241-249, 2004.
[2] C. S. Tan, R. J. Gutmann, and L. R. Reif, Wafer Level 3-D ICs Process Technology, 1st ed. New York, Springer, 2008.
[3] C. Y. Poo, B. S. Jeung, C. S. Kwang, L. S. Waf, C. M. Yu, and N. Y. Loo, "Stacked multichip module for electronic devices e.g. cellular telephone, has interconnected semiconductor packages and intervening substrate, whose outer connectors are collectively bonded by conductive elements," US6818977-B2, 2004.
[4] J. U. Meyer, T. Stieglitz, O. Scholz, W. Haberer, and H. Beutel, "High density interconnects and flexible hybrid assemblies for active biomedical implants," IEEE Transactions on Advanced Packaging, vol. 24, pp. 366-374, 2001.
[5] K. Takahashi, H. Terao, Y. Tomita, Y. Yamaji, M. Hoshino, T. Sato, T. Morifuji, M. Sunohara, and M. Bonkohara, "Current status of research and development for three-dimensional chip stack technology," Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, vol. 40, pp. 3032-3037, 2001.
[6] W. C. Lo, Y. H. Chen, J. D. Ko, T. Y. Kuo, Y. C. Shih, and S. T. Lu, "An innovative chip-to-wafer and wafer-to-wafer stacking," in 56th Electronic Components and Technology Conference (ECTC), San Diago, USA, 30 May - 2 Jun., 2006.
[7] T. Y. Kuo, S. M. Chang, Y. C. Shih, C. W. Chiang, C. K. Hsu, C. K. Lee, C. T. Lin, Y. H. Chen, and W. C. Lo, "Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost," in 58th Electronic Components and Technology Conference (ECTC), Orlando, USA, 27-30 May, 2008.
[8] K. Navas, V. S. Rao, L. Samule, W. Ho Soon, V. Lee, W. Zhang Xiao, R. Yang, and E. Liao, "Development of 3D silicon module with TSV for system in packaging," in 58th Electronic Components and Technology Conference (ECTC), Orlando, USA, 27-30 May, 2008.
[9] M. O. Bloomfield, D. N. Bentz, J. Q. Lu, R. J. Gutmann, and T. S. Cale, "Thermally induced stresses in 3D-IC inter-wafer interconnects: A combined grain-continuum and continuum approach," Microelectronic Engineering, vol. 84, pp. 2750-2756, 2007.
[10] J. Zhang, M. O. Bloomfield, J. Q. Lu, R. J. Gutmann, and T. S. Cale, "Thermal stresses in 3D IC inter-wafer interconnects," Microelectronic Engineering, vol. 82, pp. 534-547, 2005.
[11] N. Tanaka, T. Sato, Y. Yamaji, T. Morifuji, M. Umemoto, and K. Takahashi, "Mechanical Effects of Copper Through-Vias in a 3D Die-Stacked Module," in 52nd Electronic Components and Technology Conference (ECTC), San Diego, USA, 28-31 May, 2002.
[12] N. Tanaka, Y. Yamaji, T. Sato, and K. Takahashi, "Guidelines for structural and material-system design of a highly reliable 3D die-stacked module with copper through-vias," in 53rd Electronic Components and Technology Conference (ECTC), New Orleans, USA, 27-30 May, 2003.
[13] M. C. Hsieh and C. K. Yu, "Thermo-mechanical simulations for 4-layer stacked IC packages," in 9th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems (EuroSimE), Freiburg, Germany, 20-23 Apr., 2008.
[14] M. C. Hsieh and W. Lee, "FEA modeling and DOE analysis for design optimization of 3D-WLP," in 2nd Electronics System-Integration Technology Conference (ESTC), London, England, 1-4 Sep., 2008.
[15] M. C. Hsieh, C. K. Yu, and W. Lee, "Effects of geometry and material properties for stacked IC package with spacer structure," in 10th International Conference on Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems (EuroSimE), Freiburg, Germany, 26-29 Apr., 2009.
[16] S. T. Wu and M. C. Hsieh, "Design and simulation study for stacked IC packages with spacer structure," in 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), Taipei, Taiwan, 21-23 Oct., 2009.
[17] L. J. Ladani, "Numerical analysis of thermo-mechanical reliability of through silicon vias (TSVs) and solder interconnects in 3-dimensional integrated circuits," Microelectronic Engineering, vol. 87, pp. 208-215, 2010.
[18] C. C. Chiu, C. J. Wu, C. T. Peng, K. N. Chiang, T. Ku, and K. Cheng, "Failure life prediction and factorial design of lead-free flip chip package," Journal of the Chinese Institute of Engineers, vol. 30, pp. 481-490, 2007.
[19] B. Cotterell, Z. Chen, J. B. Han, and N. X. Tan, "The strength of the silicon die in flip-chip assemblies," Journal of Electronic Packaging, vol. 125, pp. 114-119, 2003.
[20] M. Y. Tsai and C. H. Chen, "Evaluation of test methods for silicon die strength," Microelectronics Reliability, vol. 48, pp. 933-941, 2008.
[21] N. McLellan, N. Fan, S. L. Liu, K. Lau, and J. S. Wu, "Effects of wafer thinning condition on the roughness, morphology and fracture strength of silicon die," Journal of Electronic Packaging, vol. 126, pp. 110-114, 2004.
[22] C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via," Microelectronic Engineering, vol. 87, pp. 505-509, 2010.
[23] J. H. Lau, Ball grid array technology. New York, McGraw-Hill, 1995.
[24] J. H. Lau, Flip chip technologies. Boston, Mass., McGraw-Hill, 1996.
[25] J. H. Lau, Electronic packaging : design, materials, process, and reliability. New York, McGraw-Hill, 1998.
[26] J. H. Lau and Y.-h. Pao, Solder joint reliability of BGA, CSP, flip chip, and fine pitch SMT assemblies. New York, McGraw-Hill, 1997.
[27] Y. T. Lin, C. T. Peng, and K. N. Chiang, "Parametric design and reliability analysis of wire interconnect technology wafer level packaging," Journal of Electronic Packaging, vol. 124, pp. 234-239, 2002.
[28] C. T. Peng, C. M. Liu, J. C. Lin, H. C. Cheng, and K. N. Chiang, "Reliability analysis and design for the fine-pitch flip chip BGA packaging," Ieee Transactions on Components and Packaging Technologies, vol. 27, pp. 684-693, 2004.
[29] M. C. Yew, C. C. Chiu, S. M. Chang, and K. N. Chiang, "A novel crack and delamination protection mechanism for a WLCSP using soft joint technology," Soldering & Surface Mount Technology, vol. 18, pp. 3-13, 2006.
[30] M. C. Yew, C. C. A. Yuan, C. J. Wu, D. C. Hu, W. K. Yang, and K. N. Chiang, "Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging," IEEE Transactions on Advanced Packaging, vol. 32, pp. 390-398, 2009.
[31] J. Y. Kim, I. S. Kang, M. G. Park, J. H. Kim, S. J. Cho, L. S. Park, and H. S. Chun, "Characterization of wafer level package for mobile phone application," in 51st Electronic Components and Technology Conference (ECTC), Orlando, USA, 29 May - 01 Jun., 2001.
[32] S. H. Dai and M. O. Wang, Reliability analysis in engineering applications. New York, Van Nostrand Reinhold, 1992.
[33] N. R. Mann, R. E. Schafer, and N. D. Singpurwalla, Methods for statistical analysis of reliability and life data. New York,, Wiley, 1974.
[34] L. F. Coffin, "A Study of the Effects of Cyclic Thermal Stress on a Ductile Metal," Transactions of ASME, vol. 76, pp. 931-950, 1954.
[35] S. S. Manson, "Behavior of materials under conditions of thermal stress," NACA TN-2933, 1954.
[36] S. S. Manson, Thermal stress and low-cycle fatigue. New York,, McGraw-Hill, 1966.
[37] H. Solomon, "Fatigue of 60/40 Solder," Components, Hybrids, and Manufacturing Technology, IEEE Transactions on, vol. 9, pp. 423-432, 1986.
[38] X. Q. Shi, H. L. J. Pang, W. Zhou, and Z. P. Wang, "Low cycle fatigue analysis of temperature and frequency effects in eutectic solder alloy," International Journal of Fatigue, vol. 22, pp. 217-228, 2000.
[39] V. Gektin, A. BarCohen, and J. Ames, "Coffin-Manson fatigue model of underfilled flip-chips," IEEE Transactions on Components Packaging and Manufacturing Technology Part A, vol. 20, pp. 317-326, 1997.
[40] J. Lau, S. Golwalkar, S. Erasmus, R. Surratt, and P. Boysan, "Experimental and Analytical Studies of 28-Pin Thin Small Outline Package (TSOP) Solder-Joint Reliability," Journal of Electronic Packaging, vol. 114, pp. 169-176, 1992.
[41] K. N. Chiang, Z. N. Liu, and P. C. Tang, "Parametric reliability analysis of no-underfill flip chip package," Components and Packaging Technologies, IEEE Transactions on, vol. 24, pp. 635-640, 2001.
[42] M. Sakurai, H. Shibuya, and J. Utsunomya, "FEM analysis of flip-chip type BGA," in 22nd IEEE/CPMT International Electronics Manufacturing Technology Symposium (IEMT-Europe), Austin, USA 27-29 Apr., 1998.
[43] R. Darveaux, "Effect of simulation methodology on solder joint crack growth correlation," in 50th Electronic Components and Technology Conference (ECTC), Las Vegas, USA, 21-24 May, 2000.
[44] R. Darveaux, "Effect of simulation methodology on solder joint crack growth correlation and fatigue life prediction," Journal of Electronic Packaging, vol. 124, pp. 147-154, 2002.
[45] R. Darveaux and K. Banerji, "Constitutive Relations for Tin-Based Solder Joints," IEEE Transactions on Components Hybrids and Manufacturing Technology, vol. 15, pp. 1013-1024, 1992.
[46] A. Yeo, C. Lee, and J. H. L. Pang, "Flip chip solder joint fatigue life model investigation," in 4th Electronics Packaging Technology Conference (EPTC), Singapore, 10-12 Dec., 2002.
[47] L. Zhang, V. Arora, L. Nguyen, and N. Kelkar, "Numerical and experimental analysis of large passivation opening for solder joint reliability improvement of micro SMD packages," Microelectronics Reliability, vol. 44, pp. 533-541, 2004.
[48] L. Zhang, R. Sitaraman, V. Patwardhan, L. Nguyen, and N. Kelkar, "Solder joint reliability model vath modified Darveaux's equations for the micro smd wafer level-chip scale package family," in 53rd Electronic Components and Technology Conference (ECTC), New Orleans, USA, 27-30 May, 2003.
[49] C. F. Lee and Y. C. Chen, "Thermodynamic formulation of endochronic cyclic viscoplasticity with damage - Application to eutectic Sn/Pb solder alloy," Journal of Mechanics, vol. 23, pp. 433-444, 2007.
[50] C. F. Lee and T. J. Shieh, "Theory of Endochronic cyclic viscoplasticity of eutectic Tin/Lead solder alloy," Journal of Mechanics, vol. 22, pp. 181-191, 2006.
[51] C. F. Lee and Z. H. Lee, "Predicting Fatigue Initiation Life of Sn/3.8Ag/0.7Cu Solder Using Endochronic Cyclic Damage-Coupled Viscoplastic Theory," Journal of Mechanics, vol. 24, pp. 369-377, 2008.
[52] C. F. Lee, Z. H. Lee, and S. H. Ou, "The Endochronic Viscoplasticity for Sn/3.9Ag/0.6Cu Solder Under Low Strain Rate Fatigue Loading Coupled With Thermal Cycling," Journal of Mechanics, vol. 25, pp. 261-270, 2009.
[53] M. J. Pfeifer, "Solder bump size and shape modeling and experimental validation," IEEE Transactions on Components Packaging and Manufacturing Technology Part B-Advanced Packaging, vol. 20, pp. 452-457, 1997.
[54] S. M. Heinrich, M. Schaefer, S. A. Schroeder, and P. S. Lee, "Prediction of solder joint geometries in array-type interconnects," Journal of Electronic Packaging, vol. 118, pp. 114-121, 1996.
[55] K. N. Chiang and W. L. Chen, "Electronic packaging reflow shape prediction for the solder mask defined ball grid array," Journal of Electronic Packaging, vol. 120, pp. 175-178, 1998.
[56] K. A. Brakke, "The Surface Evolver," Experimental Mathematics, vol. 1, pp. 141-165, 1992.
[57] K. A. Brakke, "The surface evolver and the stability of liquid surfaces," Philosophical Transactions of the Royal Society of London Series a-Mathematical Physical and Engineering Sciences, vol. 354, pp. 2143-2157, 1996.
[58] K. N. Chiang and C. A. Yuan, "An overview of solder bump shape prediction algorithms with validations," IEEE Transactions on Advanced Packaging, vol. 24, pp. 158-162, 2001.
[59] A. A. Volinsky, N. R. Moody, and W. W. Gerberich, "Interfacial toughness measurements for thin films on substrates," Acta Materialia, vol. 50, pp. 441-466, 2002.
[60] M. Menningen, H. Weiss, and U. Fischer, "Metallic Wear-Resistant Coatings for Carbon-Fiber Epoxy Composite Rolls," Surface & Coatings Technology, vol. 71, pp. 208-214, 1995.
[61] Z. G. Suo and J. W. Hutchinson, "Sandwich Test Specimens for Measuring Interface Crack Toughness," Materials Science and Engineering a-Structural Materials Properties Microstructure and Processing, vol. 107, pp. 135-143, 1989.
[62] F. Aviles and L. A. Carlsson, "Analysis of the sandwich DCB specimen for debond characterization," Engineering Fracture Mechanics, vol. 75, pp. 153-168, 2008.
[63] P. C. A. Lee, Z. X. Lima, N. Yantaraa, S. Loo, T. Y. Tee, C. M. Tan, and Z. Chen, "Fracture Toughness Assessment of a Solder Joint using Double Cantilever Beam Specimens," in 10th Electronics Packaging Technology Conference (EPTC), Singapore, 9-12 Dec., 2008.
[64] C. Atkinson, R. E. Smelser, and J. Sanchez, "Combined Mode Fracture Via the Cracked Brazilian Disk Test," International Journal of Fracture, vol. 18, pp. 279-291, 1982.
[65] J. S. Wang and Z. Suo, "Experimental-Determination of Interfacial Toughness Curves Using Brazil-Nut-Sandwiches," Acta Metallurgica Et Materialia, vol. 38, pp. 1279-1290, 1990.
[66] R. Dauskardt, M. Lane, Q. Ma, and N. Krishna, "Adhesion and debonding of multi-layer thin film structures," Engineering Fracture Mechanics, vol. 61, pp. 141-162, 1998.
[67] M. P. Hughey, D. J. Morris, R. F. Cook, S. P. Bozeman, B. L. Kelly, S. L. N. Chakravarty, D. P. Harkens, and L. C. Stearns, "Four-point bend adhesion measurements of copper and permalloy systems," Engineering Fracture Mechanics, vol. 71, pp. 245-261, 2004.
[68] M. Lane, R. H. Dauskardt, N. Krishna, and I. Hashim, "Adhesion and reliability of copper interconnects with Ta and TaN barrier layers," Journal of Materials Research, vol. 15, pp. 203-211, 2000.
[69] Q. Ma, "A four-point bending technique for studying subcritical crack growth in thin films and at interfaces," Journal of Materials Research, vol. 12, pp. 840-845, 1997.
[70] Z. H. Gan, S. G. Mhaisalkar, Z. Chen, S. Zhang, Z. Chen, and K. Prasad, "Study of interfacial adhesion energy of multilayered ULSI thin film structures using four-point bending test," Surface & Coatings Technology, vol. 198, pp. 85-89, 2005.
[71] P. G. Charalambides, J. Lund, A. G. Evans, and R. M. McMeeking, "A test specimen for determining the fracture resistarim of bimaterial interfaces," Journal of Applied Mechanics-Transactions of the Asme, vol. 56, pp. 77-82, 1989.
[72] P. G. Charalambides, H. C. Cao, J. Lund, and A. G. Evans, "Development of a Test Method for Measuring the Mixed-Mode Fracture-Resistance of Bimaterial Interfaces," Mechanics of Materials, vol. 8, pp. 269-283, 1990.
[73] M. Lane, R. H. Dauskardt, A. Vainchtein, and H. J. Gao, "Plasticity contributions to interface adhesion in thin-film interconnect structures," Journal of Materials Research, vol. 15, pp. 2758-2769, 2000.
[74] E. P. Guyer, M. Patz, and R. H. Dauskardt, "Fracture of nanoporous methyl silsesquioxane thin-film glasses," Journal of Materials Research, vol. 21, pp. 882-894, 2006.
[75] D. A. Maidenberg, W. Volksen, R. D. Miller, and R. H. Dauskardt, "Toughening of nanoporous glasses using porogen residuals," Nature Materials, vol. 3, pp. 464-469, 2004.
[76] Y. Kwon and J. Seok, "An evaluation process of polymeric adhesive wafer bonding for vertical system integration," Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers, vol. 44, pp. 3893-3902, 2005.
[77] Y. Kwon, J. Seok, J. Q. Lu, T. S. Cale, and R. J. Gutmann, "Critical adhesion energy of benzocyclobutene-bonded wafers," Journal of the Electrochemical Society, vol. 153, pp. G347-G352, 2006.
[78] W. S. Kwon, H. J. Kim, K. W. Paik, S. Y. Jang, and S. M. Hong, "Mechanical reliability and bump degradation of ACF flip chip packages using BCB (CycloteneTM) bumping dielectrics under temperature cycling," Journal of Electronic Packaging, vol. 126, pp. 202-207, 2004.
[79] Y. Kwon, A. Jindal, R. Augur, J. Seok, T. S. Cale, R. J. Gutmann, and J. Q. Lu, "Evaluation of BCB bonded and thinned wafer stacks for three-dimensional integration," Journal of the Electrochemical Society, vol. 155, pp. H280-H286, 2008.
[80] Y. Kwon, J. Seok, J. Q. Lu, T. S. Cale, and R. J. Gutmann, "Thermal cycling effects on critical adhesion energy and residual stress in benzocyclobutene-bonded wafers," Journal of the Electrochemical Society, vol. 152, pp. G286-G294, 2005.
[81] Y. Kwon, J. Seok, J. Q. Lu, T. S. Cale, and R. J. Gutmann, "Critical adhesion energy at the interface between benzocyclobutene and silicon nitride layers," Journal of the Electrochemical Society, vol. 154, pp. H460-H465, 2007.
[82] S. Y. Kook, J. M. Snodgrass, A. Kirtikar, and R. H. Dauskardt, "Adhesion and reliability of polymer/inorganic interfaces," Journal of Electronic Packaging, vol. 120, pp. 328-335, 1998.
[83] C. S. Litteken and R. H. Dauskardt, "Adhesion of polymer thin-films and patterned lines," International Journal of Fracture, vol. 119, pp. 475-485, 2003.
[84] R. Shaviv, S. Roham, and P. Woytowitz, "Optimizing the precision of the four-point bend test for the measurement of thin film adhesion," Microelectronic Engineering, vol. 82, pp. 99-112, 2005.
[85] D. M. Gage, K. Kim, C. S. Litteken, and R. H. Dauskard, "Role of friction and loading parameters in four-point bend adhesion measurements," Journal of Materials Research, vol. 23, pp. 87-96, 2008.
[86] Z. J. Cui, S. Ngo, and G. Dixit, "A sample preparation method for four point bend adhesion studies," Journal of Materials Research, vol. 19, pp. 1324-1327, 2004.
[87] B. Wang and T. Siegmund, "A modified 4-point bend delamination test," Microelectronic Engineering, vol. 85, pp. 477-485, 2008.
[88] I. Hofinger, M. Oechsner, H. A. Bahr, and M. V. Swain, "Modified four-point bending specimen for determining the interface fracture energy for thin, brittle layers," International Journal of Fracture, vol. 92, pp. 213-220, 1998.
[89] C. Litteken, R. Dauskardt, T. Scherban, G. Xu, J. Leu, D. Gracias, and B. Sun, "Interfacial adhesion of thin-film patterned interconnect structures," in 53rd Electronic Components and Technology Conference (ECTC), New Orleans, USA, 27-30 May, 2003.
[90] C. H. Tsau, S. M. Spearing, and M. A. Schmidt, "Characterization of wafer-level thermocompression bonds," Journal of Microelectromechanical Systems, vol. 13, pp. 963-971, 2004.
[91] C. H. Tsau, S. M. Spearing, and M. A. Schmidt, "Fabrication of wafer-level thermocompression bonds," Journal of Microelectromechanical Systems, vol. 11, pp. 641-647, 2002.
[92] R. Tadepalli and C. V. Thompson, "Quantitative characterization and process optimization of low-temperature bonded copper interconnects for 3-D integrated circuits," in International Interconnect Technology Conference 2003 (IITC), Burlingame, USA, 2-4 Jun, 2003.
[93] R. Tadepalli, K. T. Turner, and C. V. Thompson, "Effects of patterning on the interface toughness of wafer-level Cu-Cu bonds," Acta Materialia, vol. 56, pp. 438-447, 2008.
[94] R. Tadepalli and K. T. Turner, "A chevron specimen for the measurement of mixed-mode interface toughness of wafer bonds," Engineering Fracture Mechanics, vol. 75, pp. 1310-1319, 2008.
[95] R. Tadepalli, K. T. Turner, and C. V. Thompson, "Mixed-mode interface toughness of wafer-level Cu-Cu bonds using asymmetric chevron test," Journal of the Mechanics and Physics of Solids, vol. 56, pp. 707-718, 2008.
[96] S. Roy, E. Darque-Ceretti, E. Felder, and H. Monchoix, "Cross-sectional nanoindentation for copper adhesion characterization in blanket and patterned interconnect structures: experiments and three-dimensional FEM modeling," International Journal of Fracture, vol. 144, pp. 21-33, 2007.
[97] T. Scherban, D. Pantuso, B. Sun, S. El-Mansy, J. Xu, M. R. Elizalde, J. M. Sanchez, and J. M. Martinez-Esnaola, "Characterization of interconnect interfacial adhesion by cross-sectional nanoindentation," International Journal of Fracture, vol. 119, pp. 421-429, 2003.
[98] I. Ocana, J. M. Molina-Aldareguia, D. Gonzalez, M. R. Elizalde, J. M. Sanchez, J. M. Martinez-Esnaola, J. G. Sevillano, T. Scherban, D. Pantuso, B. Sun, G. Xu, B. Miner, J. He, and J. Maiz, "Fracture characterization in patterned thin films by cross-sectional nanoindentation," Acta Materialia, vol. 54, pp. 3453-3462, 2006.
[99] C. C. Chiu, H. H. Chang, C. C. Lee, C. C. Hsia, and K. N. Chiang, "Reliability of interfacial adhesion in a multi-level copper/low-k interconnect structure," Microelectronics Reliability, vol. 47, pp. 1506-1511, 2007.
[100] C. C. Chiu, C. C. Lee, T. L. Chou, C. C. Hsia, and K. N. Chiang, "Analysis of Cu/Low-k structure under back end of line process," Microelectronic Engineering, vol. 85, pp. 2150-2154, 2008.
[101] C. C. Lee, C. C. Chiu, C. C. Hsia, and K. N. Chiang, "Interfacial Fracture Analysis of CMOS Cu/Low-k BEOL Interconnect in Advanced Packaging Structures," IEEE Transactions on Advanced Packaging, vol. 32, pp. 53-61, 2009.
[102] C. C. Lee, T. L. Chou, C. C. Chiu, C. C. Hsia, and K. N. Chiang, "Cracking energy estimation of ultra low-k package using novel prediction approach combined with global-local modeling technique," Microelectronic Engineering, vol. 85, pp. 2079-2084, 2008.
[103] C. C. Lee, T. C. Huang, C. C. Hsia, and K. N. Chiang, "Interfacial fracture investigation of low-k packaging using J-integral methodology," IEEE Transactions on Advanced Packaging, vol. 31, pp. 91-99, 2008.
[104] M. Chiarelli and A. Frediani, "A Computation of the 3-Dimensional J-Integral for Elastic-Materials with a View to Applications in Fracture-Mechanics," Engineering Fracture Mechanics, vol. 44, pp. 763-788, 1993.
[105] W. H. Chen and C. W. Wu, "On the J-Integral for a Pressurized Crack in Bonded Materials," International Journal of Fracture, vol. 16, pp. R47-R51, 1980.
[106] W. H. Chen and Y. H. Huang, "J-Integral for Cracked Structure with Inclusions," International Journal of Fracture, vol. 15, pp. R73-R76, 1979.
[107] P. W. Claydon, "Maximum Energy-Release Rate Distribution from a Generalized 3d-Virtual Crack Extension Method," Engineering Fracture Mechanics, vol. 42, pp. 961-969, 1992.
[108] T. K. Hellen, "A Substructuring Application of the Virtual Crack Extension Method," International Journal for Numerical Methods in Engineering, vol. 19, pp. 1713-1731, 1983.
[109] S. C. Lin and J. F. Abel, "Variational Approach for a New Direct-Integration Form of the Virtual Crack Extension Method," International Journal of Fracture, vol. 38, pp. 217-235, 1988.
[110] D. M. Parks, "Virtual Crack Extension Method for Non-Linear Material Behavior," Computer Methods in Applied Mechanics and Engineering, vol. 12, pp. 353-364, 1977.
[111] T. K. Hellen, "On the Method of Virtual Crack Extension," International Journal for Numerical Methods in Engineering, vol. 9, pp. 187-207, 1975.
[112] D. M. Parks, "Stiffness Derivative Finite-Element Technique for Determination of Crack Tip Stress Intensity Factors," International Journal of Fracture, vol. 10, pp. 487-502, 1974.
[113] A. Leski, "Implementation of the virtual crack closure technique in engineering FE calculations," Finite Elements in Analysis and Design, vol. 43, pp. 261-268, 2007.
[114] A. C. Orifici, R. S. Thomson, R. Degenhardt, C. Bisagni, and J. Bayandor, "Development of a finite-element analysis methodology for the propagation of delaminations in composite structures," Mechanics of Composite Materials, vol. 43, pp. 9-28, 2007.
[115] C. Schuecker and B. D. Davidson, "Evaluation of the accuracy of the four-point bend end-notched flexure test for mode II delamination toughness determination," Composites Science and Technology, vol. 60, pp. 2137-2146, 2000.
[116] G. C. Tsai, "Parametric study of mode I energy release rate of soldered joints," Finite Elements in Analysis and Design, vol. 38, pp. 671-689, 2002.
[117] K. S. Venkatesha, B. Dattaguru, and T. S. Ramamurthy, "Finite element analysis of an interface crack with large crack-tip contact zones," Engineering Fracture Mechanics, vol. 54, pp. 847-860, 1996.
[118] K. S. Venkatesha, T. S. Ramamurthy, and B. Dattaguru, "Generalized modified crack closure integral (GMCCI) and its application to interface crack problems," Computers & Structures, vol. 60, pp. 665-676, 1996.
[119] G. S. Palani, B. Dattaguru, and N. R. Iyer, "Numerically integrated modified virtual crack closure integral technique for 2-D crack problems," Structural Engineering and Mechanics, vol. 18, pp. 731-744, 2004.
[120] R. Krueger, "Virtual crack closure technique: History, approach, and applications," Applied Mechanics Reviews, vol. 57, pp. 109-143, 2004.
[121] R. Krueger, "The Virtual crack closure technique: History, approach, and applications.," NASA/CR-2002-211628, ICASE Report No. 2002-10, 2002.
[122] M. A. J. van Gils, O. van der Sluis, G. Q. Zhang, J. H. J. Janssen, and R. M. J. Voncken, "Analysis of Cu/low-k bond pad delamination by using a novel failure index," Microelectronics Reliability, vol. 47, pp. 179-186, 2007.
[123] O. van der Sluis, R. A. B. Engelen, R. B. R. van Silfhout, W. D. van Driel, and M. A. J. van Gils, "Efficient damage sensitivity analysis of advanced Cu/low-k bond pad structures by means of the area release energy criterion," Microelectronics Reliability, vol. 47, pp. 1975-1982, 2007.
[124] C. A. Yuan, O. van der Sluis, W. D. van Driel, and G. Q. Zhang, "The need for multi-scale approaches in Cu/low-k reliability issues," Microelectronics Reliability, vol. 48, pp. 833-842, 2008.
[125] Z. W. Zhong, "Wire bonding of low-k devices," Microelectronics International, vol. 25, pp. 19-25, 2008.
[126] M. A. Meyers and K. K. Chawla, Mechanical metallurgy : principles and applications. Englewood Cliffs, N.J., Prentice-Hall, 1984.
[127] J. D. Morrow, "Cyclic Plastic Strain Energy and Fatigue of Metals," in Internal Friction, Damping, and Cyclic Plasticity, ASTM STP-378 Philadelphia, ASTM, p. 43, 1965.
[128] S. Manson, "Fatigue: A complex subject—Some simple approximations," Experimental Mechanics, vol. 5, pp. 193-226, 1965.
[129] A. Weronski and T. Hejwowski, Thermal fatigue of metals. New York, M. Dekker, 1991.
[130] W. Engelmaier, "A New Ductility and Flexural Fatigue Test Method for Copper Foil and Flexible Printed Wiring," IPC-TP-204, Institute for Interconnecting and Packaging Electronic Circuits, Evanston, USA, 1978.
[131] W. Engelmaier, "Results of the IPC copper foil ductility round-robin study," in Testing of Metallic and Inorganic Coatings, ASTM STP-947 Philadelphia, ASTM, p. 66, 1987.
[132] W. Engelmaier and A. Wagner, "Fatigue Behaviour and Ductility Determination for Roller Annealed Copper Foil and Flex Circuits on Kapton," Circuit World, vol. 14, pp. 30-38, 1988.
[133] R. Iannuzzelli, "Predicting Plated-Through-Hole Reliability in High Temperature Manufacturing Processes," in 41st Electronic Components and Technology Conference (ECTC), Atlanta, USA, 11-16 May, 1991.
[134] A. S. Prabhu, D. B. Barker, M. G. Pecht, J. W. Evans, W. Grieg, E. S. Bernard, and E. Smith, "A Thermal-Mechanical Fatigue Analysis of High Density Interconnect Vias," in Advances in electronic packaging, 1995 : proceedings of the International Intersociety Electronic Packaging Conference, INTERpack '95, New York, N.Y, ASME, p. 187, 1995.
[135] R. V. Pucha, G. Ramakrishna, S. Mahalingam, and S. K. Sitaraman, "Modeling spatial strain gradient effects in thermo-mechanical fatigue of copper microstructures," International Journal of Fatigue, vol. 26, pp. 947-957, 2004.
[136] C. Andersson, Z. Lai, J. Liu, H. Jiang, and Y. Yu, "Comparison of isothermal mechanical fatigue properties of lead-free solder joints and bulk solders," Materials Science and Engineering a-Structural Materials Properties Microstructure and Processing, vol. 394, pp. 20-27, 2005.
[137] C. Kanchanomai, Y. Miyashita, and Y. Mutoh, "Low-cycle fatigue behavior of Sn-Ag, Sn-Ag-Cu, and Sn-Ag-Cu-Bi lead-free solders," Journal of Electronic Materials, vol. 31, pp. 456-465, 2002.
[138] C. Kanchanomai and Y. Mutoh, "Low-cycle fatigue prediction model for Pb-free solder 96.5Sn-3.5Ag," Journal of Electronic Materials, vol. 33, pp. 329-333, 2004.
[139] K. O. Lee, J. Yu, T. S. Park, and S. B. Lee, "Low-cycle fatigue characteristics of Sn-based solder joints," Journal of Electronic Materials, vol. 33, pp. 249-257, 2004.
[140] C. Kanchanomai, Y. Miyashita, and Y. Mutoh, "Low-cycle fatigue behavior and mechanisms of a lead-free solder 96.5Sn/3.5Ag," Journal of Electronic Materials, vol. 31, pp. 142-151, 2002.
[141] J. K. Shang, Q. L. Zeng, L. Zhang, and Q. S. Zhu, "Mechanical fatigue of Sn-rich Pb-free solder alloys," Journal of Materials Science-Materials in Electronics, vol. 18, pp. 211-227, 2007.
[142] T. L. Anderson, Fracture mechanics: fundamentals and applications / T. L., 2nd ed., CRC Press, 1994.
[143] A. A. Griffith, "The Phenomena of Rupture and Flow in Solids," Philosophical Transactions of the Royal Society of London. Series A, vol. 221, pp. 163-198, 1921.
[144] G. R. Irwin, "Fracture Dynamics," Fracturing of Metals, American Society for Metals, Cleveland, 1948.
[145] E. F. Rybicki and M. F. Kanninen, "Finite-Element Calculation of Stress Intensity Factors by a Modified Crack Closure Integral," Engineering Fracture Mechanics, vol. 9, pp. 931-938, 1977.
[146] I. S. Raju, "Calculation of Strain-Energy Release Rates with Higher-Order and Singular Finite-Elements," Engineering Fracture Mechanics, vol. 28, pp. 251-274, 1987.
[147] K. B. Narayana, B. Dattaguru, T. S. Ramamurthy, and K. Vijayakumar, "Modified Crack Closure Integral Using 6-Noded Isoparametric Quadrilateral Singular Elements," Engineering Fracture Mechanics, vol. 36, pp. 945-955, 1990.
[148] R. Sethuraman and S. K. Maiti, "Finite-Element Based Computation of Strain-Energy Release Rate by Modified Crack Closure Integral," Engineering Fracture Mechanics, vol. 30, pp. 227-231, 1988.
[149] K. N. Shivakumar, P. W. Tan, and J. C. Newman, "A Virtual Crack-Closure Technique for Calculating Stress Intensity Factors for Cracked 3-Dimensional Bodies," International Journal of Fracture, vol. 36, pp. R43-R50, 1988.
[150] I. S. Raju, R. Sistla, and T. Krishnamurthy, "Fracture mechanics analyses for skin-stiffener debonding," Engineering Fracture Mechanics, vol. 54, pp. 371-385, 1996.
[151] J. D. Whitcomb and K. N. Shivakumar, "Strain-Energy Release Rate Analysis of Plates with Postbuckled Delaminations," Journal of Composite Materials, vol. 23, pp. 714-734, 1989.
[152] J. T. Wang and I. S. Raju, "Strain energy release rate formulae for skin-stiffener debond modeled with plate elements," Engineering Fracture Mechanics, vol. 54, pp. 211-228, 1996.
[153] M. D. Drory, M. D. Thouless, and A. G. Evans, "On the Decohesion of Residually Stressed Thin-Films," Acta Metallurgica, vol. 36, pp. 2019-2028, 1988.
[154] M. D. Thouless, A. G. Evans, M. F. Ashby, and J. W. Hutchinson, "The Edge Cracking and Spalling of Brittle Plates," Acta Metallurgica, vol. 35, pp. 1333-1341, 1987.
[155] R. Krueger and T. K. O'Brien, "Influence of Finite Element Software on Energy Release Rates Computed Using the Virtual Crack Closure Technique," NASA/CR-2006-214523, NIA Report No. 2006-06, , Oct 2006.
[156] B. D. Davidson, "An Analytical Investigation of Delamination Front Curvature in Double Cantilever Beam Specimens," Journal of Composite Materials, vol. 24, pp. 1124-1137, 1990.
[157] B. D. Davidson, R. Kruger, and M. Konig, "3-Dimensional Analysis and Resulting Design Recommendations for Unidirectional and Multidirectional End-Notched Flexure Tests," Journal of Composite Materials, vol. 29, pp. 2108-2133, 1995.
[158] B. D. Davidson, R. Kruger, and M. Konig, "3-Dimensional Analysis of Center-Delaminated Unidirectional and Multidirectional Single-Leg Bending Specimens," Composites Science and Technology, vol. 54, pp. 385-394, 1995.
[159] B. D. Davidson and R. A. Schapery, "Effect of Finite Width on Deflection and Energy-Release Rate of an Orthotropic Double Cantilever Specimen," Journal of Composite Materials, vol. 22, pp. 640-656, 1988.
[160] I. S. Raju, J. H. Crews, and M. A. Aminpour, "Convergence of Strain-Energy Release Rate Components for Edge-Delaminated Composite Laminates," Engineering Fracture Mechanics, vol. 30, pp. 383-396, 1988.
[161] I. S. Raju, K. N. Shivakumar, and J. H. Crews, "3-Dimensional Elastic Analysis of a Composite Double Cantilever Beam Specimen," AIAA Journal, vol. 26, pp. 1493-1498, 1988.
[162] J. H. Crews, K. N. Shivakumar, and I. S. Raju, "Strain-Energy Release Rate Distributions for Double Cantilever Beam Specimens," AIAA Journal, vol. 29, pp. 1686-1691, 1991.
[163] J. M. Gere and B. J. Goodno, Mechanics of materials, 7th ed. Toronto, ON ; Clifton Park, NY, Cengage Learning, 2009.
[164] A. Polyakov, M. Bartek, and J. N. Burghartz, "Area-selective adhesive bonding using photosensitive BCB for WL CSP applications," Journal of Electronic Packaging, vol. 127, pp. 7-11, 2005.
[165] J. M. Snodgrass, D. Pantelidis, M. L. Jenkins, J. C. Bravman, and R. H. Dauskardt, "Subcritical debonding of polymer/silica interfaces under monotonic and cyclic loading," Acta Materialia, vol. 50, pp. 2395-2411, 2002.
[166] R. Iannuzzelli, "Predicting plated-through-hole reliability in high temperature manufacturing processes," presented at the 41st Electronic Components and Technology Conference (ECTC), Atlanta, USA, 11-16 May, 1991.
[167] "Temperature Cycling," JEDEC JEDS22-A104-B, p. EIA & JEDEC Solid State Technology Association, 2000.
[168] K. Tanida, M. Umemoto, N. Tanaka, Y. Tomita, and K. Takahashi, "Micro Cu bump interconnection on 3D chip stacking technology," Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers, vol. 43, pp. 2264-2270, 2004.
[169] P. L. Liu and J. K. Shang, "Influence of microstructure on fatigue crack growth behavior of Sn-Ag solder interfaces," Journal of Electronic Materials, vol. 29, pp. 622-627, 2000.