|
[1] R. E. Best, Phase-Locked Loops Design, Simulation, and Applications, 4th ed. New York: McGraw-Hill, 1999. [2] C. S. Vaucher, “An adaptive PLL tuning system architecture combining high spectral purity and fast settling time,” IEEE J. Solid-States Circuits, Vol. 35, Issue 4, pp. 490-502, April 2000. [3] J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control, “ IEEE J. Solid-States Circuits, Vol. 35, Issue 8, pp. 1137-1145, Aug. 2000. [4] S. Sidiropoulos, D. Liu, J. Kim, G. Wei and M. Horowitz, “Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers,” Proc. of Symp. on VLSI Circuits Dig. of Tech. Papers, pp. 124-127, June 2000. [5] J. Hakkinen, J. Kostamovaara, “Speeding up an integer-N PLL by controlling the loop filter charge,” IEEE Transactions, Analog and Digital Signal Processing, Circuits and Systems, Vol. 50, Iss. 7, pp. 343-354, July 2003. [6] L. Liu, B. Li, “Reduced pull-in time of phase-locked loops with a novel nonlinear phase-frequency detector,” Proc. of Microwave Conference, Proc. of Asia-Pacific Conf. Vol. 5, Dec. 2005. [7] Y. F. Kuo, R. M. Weng, Chuan-Yu Liu, “A Fast Locking PLL With Phase Error Detector,” Conf. of Electron Devices and Solid-State Circuits, pp. 423-426. Dec. 2005. [8] C. Y. Yang; S. I. Liu, “Fast-switching frequency synthesizer with a discriminator-aided phase detector,” IEEE Journal of Solid-State Circuits, Vol. 35, Iss.10, pp. 1445-1452, Oct. 2000. [9] K. H. Cheng, W. B. Yang, Cheng-Ming Ying, “A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop,” IEEE Transactions, Analog and Digital Signal Processing, Circuits and Systems, Vol. 50, Iss. 11, pp. 892-896, Nov. 2003. [10] Y. S. Choi, H. H. Choi, T. H. Kwon, “An adaptive bandwidth phase locked loop with locking status indicator,” Proc. KORUS, Science and Technology, pp. 826-829, June 2005. [11] K. Woo, Y. Liu, E. Nam, and D. Ham, “Fast-Lock Hybrid PLL Combining Fractional-N and Integer-N Modes of Differing Bandwidths,” IEEE Jounal of Solid--State Circuits, Vol. 43, No. 2, pp. 379-389, Feb. 2008. [12] T. Xia, J.C. Lo, “Time-to-voltage converter for on-chip jitter measurement,” IEEE Transactions on Instrumentation and Measurement, Vol. 52, Iss. 6, pp. 1738-1748, Dec. 2003. [13] J.G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE Journal of Solid-State Circuits, Vol. 31, Iss. 11, pp. 1723-1732, Nov. 1996. [14] E. J. Hernandez, A. Diaz Sanchez, “Positive feedback CMOS charge-pump circuits for PLL applications,” Proc. of the 44th IEEE 2001 Midwest Symposium, MWSCAS, Circuits and Systems, Vol. 2, pp. 836-839, Aug. 2001. [15] S. Pellerano, S. Levantino, C. Samori, and A. L. Lacaita, “A dual-band frequency synthesizer for 802.11a/b/g with fractional-spur averaging technique,” in IEEE ISSCC Dig. Tech. Papers, Vol. 1, pp. 104–105. Feb. 2005. [16] B. Memmler, E. Gotz, and G. Schonleber, “New fast-lock PLL for mobile GSM GPRS applications,” in Proc. 26th ESSCIRC, pp. 468–471. Sep. 2000
|