當製成技術不斷的演進，靜態隨機存取記憶體電路設計會著重於低電壓和高速的目標去設計。然而，對於低電壓記憶體電路設計，寫入失敗和讀取干擾的問題會限制住傳統6電晶體(6T)靜態隨機存取記憶體的最低操作電壓，因此才需要去設計良好的寫入能力跟讀取能力的記憶體胞。

在此篇論文中，我們提出新穎單電源8電晶體(8T)靜態隨機存取記憶體。8T隨機存取記憶體是利用不同的電壓偏壓來供給記憶體胞，此設計可以用來幫助資料成功寫入記憶體胞。而8T隨機存取記憶體的電路結構也採用位元線來供給記憶體胞電壓。另外，為了提高8T靜態隨機存取記憶體讀取的穩定性，我們也提出提高位元線的電路設計來配合應用在8T隨機存取記憶體上。提高位元線相當於提高8T隨機存取記憶體的供給電壓，進而來改善讀取靜態雜訊邊界。利用提高位元線電路設計與傳統6T隨機存取記憶體比較，可以改善19.7%讀取靜態雜訊邊界在供給電壓為0.5V時。為了設計在奈米製成技術和低功率下，我們也採用了分割位元線和分割位址線架構來實現我們的晶片設計，利用分割位元線和分割位址線架構，可以分別增快寫入和讀取的速度。更進一步，我們用45奈米CMOS技術製作39Kb靜態隨機存取記憶體晶片，並且量測出8T靜態隨機存取記憶體的最低供給電壓低於6T靜態隨機存取記憶體的最低供給電壓210mV。

　　Write failure and read disturb limited the minimum operation voltage (VDDmin) of SRAM. We proposed a single supply 8-transistor SRAM cell with improved write margin (WM) and read-static noise margin (RSNM) to achieve low operation voltage.The proposed 8T SRAM cell employ differential data-aware supply voltage, which is supplied by a bitline pair, to enlarge its write margin. In addition, a bitline-boost scheme is proposed to improve read stability of the proposed 8T cell. Two 39Kb SRAM macros, 6T and proposed 8T, were fabricated using a 45nm CMOS technology. The measured VDDmin of our 8T SRAM macro is 210mV lower than that of 6T SRAM macro.

1 Introduction 1
1.1 Challenge for Low-Voltage SRAM Cell . . . . . . . . . . . . . . . . . 1
1.2 Structure of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Issues of 6T SRAM at Low-Voltage 3
2.1 Write/Read Operation of Conventional 6T SRAM . . . . . . . . . . . . 3
2.2 Write Margin of Low VDD . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Static-Noise-Margin of Low VDD . . . . . . . . . . . . . . . . . . . . 6
2.4 SRAM Cells with Write Assist . . . . . . . . . . . . . . . . . . . . . . 8
2.4.1 Differential-VDDM Cell . . . . . . . . . . . . . . . . . . . . . 8
2.4.2 Portless 5T SRAM Cell . . . . . . . . . . . . . . . . . . . . . 10
3 Proposed 8T SRAM Cell 12
3.1 8T SRAM Cell Description . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1 SNM Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.2 RSNM with BL Voltage decreasing . . . . . . . . . . . . . . . 17
3.4 Read Operation with Boost Bit-Line . . . . . . . . . . . . . . . . . . . 18
3.4.1 Icell Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.2 RSNM with Boost Bit-Line . . . . . . . . . . . . . . . . . . . 20
3.5 8T SRAM Cell Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 SRAM Macro Implementation 25
4.1 Macro Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.1 Conventional SRAM Architecture . . . . . . . . . . . . . . . . 25
4.1.2 Macro-1 Architecture for Proposed 8T SRAM . . . . . . . . . 27
4.1.3 DividedWL and BL Structure . . . . . . . . . . . . . . . . . . 28
4.1.4 Macro-2 Architecture for Proposed 8T SRAM . . . . . . . . . 30
4.2 Block Description and Data Line Bus . . . . . . . . . . . . . . . . . . 30
4.2.1 Select and Unselect Blocks . . . . . . . . . . . . . . . . . . . . 30
4.2.2 HSNM during Float Phenomenon . . . . . . . . . . . . . . . . 31
4.2.3 Data Line Bus . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3 Macro Layout for Proposed 8T SRAM . . . . . . . . . . . . . . . . . . 34
4.4 Testchip Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 Comparison and Experimental Results 39
5.1 Comparison with 6T . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.1 Statistical Simulation for WM . . . . . . . . . . . . . . . . . . 39
5.1.2 Statistical Simulation for RSNM with BL Voltage decreasing . . 40
5.2 Comparison with Other W-Assist Cell . . . . . . . . . . . . . . . . . . 41
5.2.1 Comparison with 5T Portless SRAM Cell . . . . . . . . . . . . 41
5.2.2 Comparison with Differential-VDDM 6T SRAM Cell . . . . . 43
5.2.3 Macro Area Penalty . . . . . . . . . . . . . . . . . . . . . . . 44
5.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.1 Testchip Photo . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.2 Shmoo Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6 Conclusions and Future Work 48
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

[1] E. Seevinck et al., “Static-noise margin analysis of MOS SRAM cells,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-22, no. 2, pp. 748–754, May 1987.
[2] Benton H. Calhoun, and Anantha P. Chandrakasan, “Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 7, JULY 2006.
[3] Evelyn Grossar, Michele Stucchi, Karen Maex, and Wim Dehaene, “Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006.
[4] Benton H. Calhoun, and Anantha P. Chandrakasan, “A 256-kb 65-nm Subthreshold SRAM Design for Ultra-Low-Voltage Operation,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 3, MARCH 2007.
[5] M.Wieckowski, S. Patil, and M.Margala, “Portless SRAM—A High-Performance Alternative to the 6T Methodology,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 11, NOVEMBER 2007.
[6] H. YAMAUCHI, T. SUZUKI, and Y. YAMAGAMI, “A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation,” IEICE TRANS. ELECTRON., VOL.E89–C, NO.11 NOVEMBER 2006.
[7] H. YAMAUCHI, T. SUZUKI, and Y. YAMAGAMI, “A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses,” IEICE TRANS. ELECTRON., VOL.E90–C, NO.4 APRIL 2007.
[8] T.Suzuki, H. Yamauchi, Y. Yamagami, K. Satomi, and H. Akamatsu, “A Stable 2-Port SRAMCell Design Against Simultaneously Read/Write-Disturbed Accesses,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008.
[9] K. Kanda,H. Sadaaki, and T. Sakurai, “90% Write Power-Saving SRAM Using Sense-Amplifying Memory Cell,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004.
[10] K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T.Ishii, and H. Kobatake, “A read-static-noise-margin-free SRAM cell for low-Vdd and high-speed applications,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 41, no. 1, pp.113–121, Jan. 2006.
[11] Ik Joon Chang1 Jae-Joon Kim, Sang Phill Park, Kaushik Roy, “A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS,” IEEE International Solid-State Circuits Conference, February 5,2008.
[12] M. Yoshimoto et al., “A divided word-line structure in the static RAM and its application to a 64k full CMOS RAM,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-18, pp. 479-485, Oct. 1983.
[13] T. HIROSE et al., “A 20-ns 4-Mb CMOS SRAM with HierarchicalWord Decoding Architecture,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 5, OCTOBER 1990.
[14] Byung-Do Yang and Lee-Sup Kim, “A Low-Power SRAM Using Hierarchical Bit Line and Local Sense Amplifiers, IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 40, NO. 6, JUNE 2005.
[15] J. Davis et al., “A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor,” IEEE International Solid-State Circuits Conference, February 2006.
[16] Ashish Karandikar and Keshab K Parhi, “Low Power SRAM Design using Hierarchical Divided Bit Line Approach,”Computer Design: VLSI in Computers and Processors, 1998. ICCD ’98.
[17] Ravishankar Rao, Justin Wenck, Diana Frankliny, Rajeevan Amirtharajah and Venkatesh Akella, “Segmented Bitline Cache: Exploiting Non-Uniform Memory Access Patterns,” Lecture Notes in Computer Science.
[18] M. Yamaoka et al., “0.4-V logic library friendly SRAM array using rectangulardiffusion cell and delta-boosted-array-voltage scheme,” in Symp. VLSI Circuits Dig., Jun. 2002, pp. 170–173.
[19] A. J. Bhavnagarwala et al., “A transregional CMOS SRAM with single, logic VDD and dynamic power rails,” in Symp. VLSI Circuits Dig., Jun. 2004, pp. 292–293.
[20] E. Grossar, M. Stucchi, K. Maex, and W. Dehaene, “Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006.
[21] Jaydeep P. Kulkarni,K. Kim, and K. Roy, “A 160mV Robust Schmitt Trigger Based Subthreshold SRAM,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 10, OCTOBER 2007.
[22] K. Nii et al., “A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations,” IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL. 43, NO. 1, JANUARY 2008.
[23] Fang-shi Lai and Chia-Fu Lee, “On-Chip Voltage Down Converter to Improve SRAM Read/Write Margin and Static Power for Sub-Nano CMOS Technology,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007.