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Reference [1] M. Simek, I. Mica, J. Kacalek, and R. Burget, “Bandwidth Efficiency of Wireless Networks of WPAN WLAN WMAN and WWAN,” Electrotechnic Magazine ISSN 1213-1539, Aug. 28, 2007. [2] ”EWC HT PHY Specification,” Enhanced Wireless Consortium, Dec. 2005. [3] WiMAX Forum, Mobile WiMAX-Part I: A technical overview and performance evaluations, Feb. 21, 2006. [4] Bingham, “Multicarrier Modulation for Data Transmission: An Idea Whose Time Has Come,” IEEE Trans. Communications Magazine, vol. 28, pp. 5-14, May. 1990. [5] Cimini, L., Jr., “Analysis and Simulation of a Digital Mobile Channel Using Orthogonal Frequency Division Multiplexing, “ IEEE Trans. Communications Magazine, vol. 33, pp. 665-675, Jul. 1985. [6] A. Peled and A. Ruiz, “Frequency domain data transmission using reduced computational complexity algorithms,” In Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, vol. 5, pp. 964-967, Apr. 1980. [7] O. Edfors, M. Sandell, J.-J. van de Beek, D. Landstrom, and F. Sjoberg, “An introduction to orthogonal frequency-division multiplexing,” Lulea Univ. Technol., Lulea, Sweden, Res. Rep./1996:16, 1996. [8] J. W. Cooley and J. W. Tukey, “An Algorithm for Machine Computation of Complex Fourier Series, “ Math. Computation, vol. 19, pp. 297-301, April 1965. [9] S. He and M. Torkelson, “Design Pipeline FFT Processor for OFDM (de)Modulation,” IEEE Signals, Systems, and Electronics, pp. 257-262, Oct. 1998. [10] P. Duhamel and H. Hollmann, “Split Radix FFT Algorithm,” Electronics Letters, vol. 20, pp.14-46, Jan. 5, 1984. [11] L. Jia, Y. Gao, J. Isoaho, and H. Tenhunen, “A new VLSI-oriented FFT algorithm and implement,” in Proc. 11th Annual IEEE Int. ASIC Conf., pp. 337-341, Sep. 1998. [12] H. Shousheng and M. Torkelson, “Designing pipeline FFT processor for OFDM (de)modulation,” in Proc. Int. Symp. Signals, Syst., and Electronics, vol. 29, pp. 257–262, Oct. 1998. [13] G. Bi and E.V. Jones, “A pipelined FFT processor for word-sequential data,” In Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, vol. 37, pp.1982-1985, Dec. 1989. [14] S.-M. Kim, J.-G. Chung, and K.K. Parhi, ”Low error fixed-width CSD multiplier with efficient sign extension,” IEEE Trans. Circuits Syst. II, vol., pp.984-993, Dec. 2003. [15] B.-G. Jo and M.-H. Sunwoo, "New continuous-flow mixed radix (CFMR) FFT using novel in-place strategy," IEEE Trans. Circuits Syst., vol. 52, pp. 911-919, May. 2005. [16] Y. Chen, Y.-W. Lin and C.-Y Lee, “A Block Scaling FFT/IFFT Processor for WiMAX Applications,” In Proc. IEEE Asian Solid-State Circuits Conf., pp. 203-206, Nov. 2006. [17] G. Zhong, F. Xu, and A. N. Willson Jr., "A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring," IEEE J. Solid-State Circuits, vol. 41, pp. 483-495, Feb. 2006. [18] Y.-T. Lin, P.-Y. Tsai, and T.-D. Chiueh, "Low-power variablelength fast Fourier transform processor," In Proc. Comput. Digit. Tech., vol. 152, no. 4, pp. 499-506, July 2005. [19] B. M. Bass, “A low-power, high-performance, 1024-point FFT processor,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 380–387, Mar.1999. [20] Y. Chen, Y.-C. Tsao, Y-W. Lin, C.-H. Lin and C.-Y. Lee, “An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications,” IEEE Trans. Circuits and Systems II, vol. 55, pp.146-150, Feb. 2008. [21] Y.-W. Lin, H.-Y. Liu, and C.-Y. Lee, “A dynamic scaling FFT processor for DVB-T applications,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2005–2013, Nov. 2004.
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