In this thesis we present a 1.25-Gb/s fully cell-based all-digital clock and data recovery (ADCDR) circuit with a half-rate duty-cycle-tolerance digital quadricorrelator frequency detector (DQFD). By applying the half-rate CDR circuit, we only need to provide 625MHz clock to recover the 1.25-Gb/s incoming NRZ data stream. Simulation results show that the proposed half-rate DQFD is able to generate up and down signals for adjusting Digital Controlled Oscillator (DCO) correctly by using multiphase clock signals with duty-cycle from 14% to 85%. Besides, we use a frequency-enhancement circuit to apply binary search algorithm for frequency acquisition. The frequency acquisition is stopped when binary search ends or a frequency-lock signal is generated from the frequency-locked detector (LD). By a digital controlled oscillator (DCO) and an all-digital delay-locked loop (ADDLL), we are able to generate eight multiphase clock signals with different frequencies for different blocks in our proposed ADCDR circuit and use a half-rate Bang-Bang phase detector (PD) as our half-rate PD. Furthermore, we can track the phase between the incoming NRZ data stream and recovered clock correctly and reduce the jitter of recovered clock by using a suppressive filter. Finally, the recovered data is regenerated by a decision making circuit. The post-layout simulation results show the RMS jitter and perk-to-peak jitter of recovered clock are 5.37ps (0.336%UI) and 29.5ps (1.84%UI) respectively when we use the pseudorandom bit sequence (PRBS) of 27-1 to generate the incoming NRZ data stream. The average recovered clock frequency is 625.05MHz.

在這篇論文裡面，我們提出了一個具有容忍工作週期 (duty-cycle) 之半速率數位頻率偵測器 (digital quadricorrelator frequency detector) 且運用在每秒12.5億位元並利用TSMC 0.18μm之標準元件庫來設計的全數位時脈與數據恢復電路(clock and data recovery circuit)。藉由採用半速率的時脈與數據恢復電路架構，我們只需要提供頻率為625MHz的多相位時脈來恢復每秒12.5億位元的數據。實驗模擬結果顯示我們所設計的半速率數位頻率偵測器可以在多相位時脈的工作週期為14%到85%之下正確地產生給數位震盪器調整頻率的up和down訊號。除此之外我們還引用了一個增加頻率判斷可信度的電路，藉此採用二元式的頻率搜尋理論。當二元式的頻率搜尋理論結束或是頻率鎖定偵測器產生了鎖定的訊號時，頻率搜尋過程即終止。藉由搭配運用數位頻率震盪器與數位延時鎖定回路，我們可以產生不同頻率的多相位時脈給我們所設計之全數位時脈與數據恢復電路中的不同區塊來運用，並且使用了一個半速率的Bang-Bang相位偵測器來當作我們的半速率相位偵測器。此外我們並使用了一個具壓抑性的數位濾波器來正確地追蹤數據與被恢復的時脈之相位並且減少被恢復的時脈之抖動量。最後藉由一個取樣器來產生被恢復的數據。經過佈局後之實驗模擬結果顯示，當我們使用27-1之虛擬亂數數據序列 (Pseudorandom bit sequence) 來產生我們的隨機資料時，其方均根抖動量與峰對峰抖動量分別為5.42ps (0.34%UI)與29.5ps (1.84%UI)。恢復的平均時脈週期為625.05MHz.

Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Motivation 1
1.3 Thesis Organization 2
Chapter 2 Preliminaries 3
Chapter 3 Circuit Architecture 9
3.1 Overall Architecture 9
3.2 Digitally Controlled Oscillator 10
3.3 Digital QuadriCorrelator Frequency Detector 12
3.4 ALL- Digital Controlled Delay-Locked Loop 18
3.5 Enhancement Circuit 19
3.6 The Frequency-Locked Detector Circuit 20
3.7 The Phase Detector 21
3.8 Suppressive Filter 22
3.9 The Duty-Cycle Corrector 24
3.10 The Decision Making Circuit 26
3.11 The Overall CDR Operation Flow 28
Chapter 4 Experimental Results 31
4.1 Pre-Layout Simulation Results 31
4.2 Post-Layout Simulation Results 33
Chapter 5 Conclusion 39
Bibliography 40
Acknowledgement 44

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