|
1. R. R. Tummala, Fundamentals of Microsystems Packaging, McGraw-Hill, New York, 2001. 2. V. Kripesh, S. W. Yoon, V. P. Ganesh, N. Khan, M. D. Rotaru, W. Fang and M. K. Iyer, “Three-Dimension System-in-Package using Stacked Silicon Platform Technology,” IEEE Transactions on Advanced Packaging, Vol. 28, pp. 377-386, 2005. 3. 奈米電子共同實驗室使用者聯盟,產業要聞與分析,SoC發展面臨瓶頸,造就SiP發展方向被看好,2004. 4. http://ssttpro.acesuppliers.com/semiconductor/Magazine_Details_Index_Id_70.html. J. Adam, M. Bird, 系統封裝技術(SiP)提供設計之選擇-技術整合和降低成本,半導體科技雜誌導讀,AP封面故事,2005。 5. M. D. Samber, T. Nellissen and E. V. Grunsven, “Through Wafer Interconnection Technologies for Advanced Electronic Devices,” IEEE Electronics Packaging Technology Conference, pp.1-6, 2004. 6. J. U. Knickerbocker, L. P. Buchwalter, E. J. Sprogis, H. Gan, R. R. Horton, R. J. Dolastre, S. L. Wrigh and J. Cotte, “3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias,” IEEE Journal of Solid-State Circuits, Vol. 41, pp. 1718-1725, 2006. 7. http://auo.com/auoDEV/technology.php?sec=COG&ls=tc. 8. T. H. Wang, C. C. Lee, Y. S. Lai and Y. C. Lin, “Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions,” ASME Journal of Electronic Packaging, Vol. 128, pp. 281-284, 2006. 9. T. T. Yan, M. Lim, N. H. Shen, X. Barato, D. Kaire and Z. Zhaowei, “Design Analysis of Solder Joint Reliability for Stacked Die Mixed Flip-Chip and Wirebond BGA,” IEEE Electrical Packaging Technology Conference, pp. 391-397, 2002. 10. B. A. Zahn, “Finite Element Based Solder Joint Fatigue Life Predictions for a Same Die Size-Stacked-Chip-Scale-Ball Grid Array Package,” IEEE Electronics Manufacturing Technology Symposium, pp. 274-284, 2002. 11. S. X. Wu, J. Chin, T. Grigorich, X. Wu, G. Mui and C. P. Yeh, “Reliability Analysis for Fine Pitch BGA Package,” IEEE Electronic Components and Technology Conference, pp. 737-741, 1998. 12. T. Burnette, Z. Johnson, T. Koschmieder and W. Oyler, “Underfilled BGAs for Ceramic BGA Packages and Board-Level Reliability,” IEEE Electronic Components and Technology Conference, pp. 1221-1226, 2000. 13. S. Y. Teng and M. Brillhart, “Reliability Assessment of a High CTE CBGA for High Availability Systems,” IEEE Electronic Component and Technology Conference, pp. 611-616, 2002. 14. 李英舜,塑封球柵陣列電子封裝之破裂延伸,國立清華大學動力機械工程學系碩士論文,2000。 15. J. H. L. Pang, K. H. Tan, X. Shi and Z. P. Wang, “Thermal Cycling Aging Effects on Microstructual and Mechanical Properties of a Single PBGA Solder Joint Specimen,” IEEE Transactions on Components and Packaging Technology, Vol. 24, pp. 10-15, 2001. 16. B. Han, M. Chopra, S. Park, L. Li and K. Veima, “Effect of Substrate CTE on Solder Ball Reliability of Flip-Chip PBGA Package Assembly,” Journal of Surface Mount Technology, Vol. 9, pp. 43-52, 1996. 17. 蔡嘉育,覆晶構裝底填膠材料機械性質及可靠度分析,國立清華大學動力機械工程學系碩士論文,2002。 18. J. H. Lau, “Solder Joint Reliability of Flip Chip and Plastic Ball Grid Array Assemblies under Thermal, Mechanical, and Vibrational Conditions,” IEEE Transactions on Components, Packaging and Manufacturing Technology-Part B, Vol. 19, pp. 728-735, 1996. 19. Y. Cheng, G. Xu, D. Zhu, X. Lin, and L. Luo, “Thermo- Mechanical Reliability Study of High I/Os Flip Chip on Laminated Substrate Based on FEA, RSM and Interfacial Fracture Mechanics,” 6th International Conference on Electronic Packaging Technology, pp. 459-466, 2005. 20. S. Y. Jang, T. S. Park, Y. S. Kim, J. W. Jeong, J. J. Bang, D. K. Kang, “Wafer Level Package Solder Joint Reliability Study for Portable Electronic Devices,” Electronic Component and Technology Conference, pp. 660-664, 2005. 21. N. Ranganathan, K. Prasad, N. Balasubramanian, Z. Qiaoer and S. C. Hwee, “High Aspect Ratio Through-Wafer Interconnect for Three Dimensional Integrated Circuits,” IEEE Electronic Components and Technology Conference, pp. 343-348, 2005. 22. P. A. Miranda, A. J. Moll, “Thermo-Mechanical Characterization of Copper Through-Wafer Interconnects,” IEEE Electric Components and Technology Conference, pp. 844- 848, 30 May-2 June 2006. 23. S. Spiesshoefer, J. Patel, T. Lam, L. Cai, S. P. R. F. Figueroa, S. L. Burkett, L. Schape, R. Geil and B. Roger, “Copper Electroplating to Fill Blind Vias for Three-Dimensional Integration,” The Journal of Vacuum Science and Technology A, Vol. 24, pp. 1277-1282, 2006. 24. S. Spiesshoefer, L. Schaper, S. Burkett, G. Vangara, Z. Rahman and P. Arunasalam, “Z-Axis Interconnects Using Fine Pitch, Nanoscale Through-Silicon Vias: Process Development,” IEEE Electronic Components and Technology Conference, Vol. 1, pp. 466-471, 2006. 25. A. Parthihan, Z. Fan, A. D. Harold, S. G. Bahgat, “Thermo-Mechanical Analysis of Thru-Silicon-Via Based High Density Compliant Interconnect,” Electronic Components and Technology Conference, pp. 1179-1185, 2007. 26. C. W. Lin, H. A. Yang, W. C. Wang, W. L. Fang, “Implementation of Three-Dimensional SOI-MEMS Wafer-Level Packaging Using Through-Wafer Interconnections,” Journal of Micromechanics and Microengineering, Vol. 17, pp. 1200-1205, 2007. 27. T. E. Lawrence, S. M. Donovan, W. B. Knowltonl, J. R. Byers and A. J. Moll, “Electrical Characterization of Through-Wafer Interconnects,” IEEE Workshop Microelectronics and Electron Devices, pp. 99-102, 2004. 28. S. W. Yoon, D. Witarsa, S. Y. L. Lim, V. Ganesh, A. G. K. Viswanath, T. C. Chai, K. O. Navas and V. Kripesh, “Reliability Studies of a Through Via Silicon Stacked Module for 3D Microsystem Packaging,” IEEE Electronic Components and Technology Conference, pp. 1449- 1453, 30 May-2 June 2006. 29. N. Khan, S. W. Yoon, A. G. K. Viswanath, V. P. Ganesh, Ranganathan, D. Witarsa, S. Lim, “Development of 3D Stack Package Using Silicon Interposer for High Power Application,” IEEE Electronic Components and Technology Conference, pp. 756- 760, 30 May-2 June 2006. 30. K. O. Lee, K. E. Ong, K. N. Seetharamu, I. A. Azid and G. A. Quadir, “Application of Artificial Intelligence for the Determination of Package Parameters for a Desired Solder Joint Fatigue Life,” Microelectronics International, Vol. 23, pp. 37-44, 2006. 31. R. G. Filippi, J. F. McGrath, T. M. Shaw, C. E. Murray, H. S. Rathore, P. S. McLaughlin, V. McGahay, L. Nicholson, P. C. Wang, J. R. Lloyd, M. Lane, R. Rosenberg, X. Liu, Y. Y. Wang, W. Landers, T. Spooner, J. J. Demarest, B. H. Engel, J. Gill, G. Goth, E. Barth, G. Biery, C. R. Davis, R. A. Wachnik, R. Goldblan, T. Ivers, A. Swinton, C. Barile, and J. Aitken, “Thermal Cycle Reliability of Stacked Via Structures with Copper Metallization and an Organic Low-k Dielectric,” IEEE 42nd Annual International Reliability Physin Sympasiur, pp. 61-67, 2004. 32. N. Tanaka, T. Sato, Y. Yamaji, T. Morifuji, M. Umemoto and K. Takahashi, “Mechanical Effects of Copper Through-Vias in a 3D Die-Stacked Module,” IEEE Eletronic Components and Technology Conference, pp. 473-479, 2002. 33. P. Benkart, A. Kaiser, A. Munding, M. Bschorr, H. J. Pfleiderer, E. K. A. Heittmann, H. Huebner and U. Ramacher, “3D Chip Stack Technology Using Through-Chip Interconnects,” IEEE Design and Test of Computers, pp. 512-518, 2005. 34. X. Chen, J. Zhang, Z. P. Wang, “Microscopic Observation of Failure Mechanism of Anisotropic Conductive Film for Flip-Chip Joining,” IEEE Inter Society Conference on Thermal Phenomena, pp. 453-457, 2004. 35. C. W. Lin, C. P. Hsu, H. A. Yang, W. C. Wang, and W. L. Fang, “Implement of SOG Devices with Embedded Through-Wafer Silicon Vias Using a Glass Reflow Process for Wafer-Level 3D MEMS Integration,” in Proceedings of 21st IEEE International Conference on Micro Electro Mechanical Systems, pp. 802-805, January 13-17, 2008. 36. Fraunhofer ISIT, Itzehoe (DE) “Electrical Feedthroughs Using Wafer-Level Glass-Flow Technology,” Achievements and Results AnnualReport, pp. 36-39, 2005. 37. C. M. L. Wu, M. L. Chau, “Degradation of Flip-Chip-on-Glass Interconnection with ACF under High Humidity and Thermal Aging,” Soldering and Surface Mount Technology, Vol. 14, pp. 51-58, 2002. 38. R. Joshi, “Chip on Glass-Interconnect for Row/Column Driver Packaging,” Microelectronics Journal, Vol. 29, No.6, pp. 343-349, 1998. 39. M. Ebert, J. Bagdahn, “Determination of Residual Stress in Glass Frit Bonded MEMS by Finite Element Analysis,” 5th. Int. Conf. on Thermal and Mechanical Simulation and Experiments in Micro-electronics and Micro-System, pp. 407-412, 2004. 40. P. Merz, H. J. Quenzer, H. Bernt, B. Wagner, M. Zoberbier, “A Novel Micromachining Technology for Structuring Borosilicate Glass Substrates,” IEEE Transducers, Vol. 1, pp. 258-261, 2003. 41. W. N. Sharpe, Jr., D. A. LaVan, and R. L. Edwards, “Mechanical Properties of LIGA-Deposited Nickel for MEMS Transducers,” International Conference on Solid-State Sensors and Actuators, pp. 607-610, June 16-19, 1997. 42. T. Fritz, H. S. Cho, K. J. Hemker, W. Mokwa, and U. Schnakenberg, “Characterization of Electroplated Nickel,” Microsystem Technologies, Vol. 9, pp.87-91, 2002. 43. H. S. Cho, K. J. H. Hemker, K. Lian, J. Goettert, and G. Dirras, “Measured Mechanical Properties of LIGA Ni Structures,” 15th IEEE MEMS conference, Sensors and Actuators A 103, pp.59-63, 2003. 44. R. Liu, H. Wang, X. Li, G. Ding, and C.Yang, “A Micro-Tensile Method for Measuring Mechanical Properties of MEMS Materials,” Journal of Micromechanics and Microengineering, pp. 1-7, 2008. 45. ANSYS Release 10.0, ANSYS, Inc., PA, 2005. 46. R. D. Cook, D. S. Malkus, M. E. Plesha, R. J. Witt, Concepts and Applications of Finite Element Analysis, 4th ed., John Wiley & Sons, Inc., Danvers, 2002. 47. 康淵,陳信吉,ANSYS入門,全華科技圖書股份有限公司,台北。 48. J. H. Lienhard, A Heat Transfer Textbook, 2nd ed., Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1987. 49. G. R. Blackwell, The Electronic Packaging Handbook, CRC Press, Boca Raton, 2000. 50. 李輝煌,田口方法品質設計的原理與實務,高立圖書有限公司,台北,2000。 51. 黎正中譯,穩健設計之品質工程,台北圖書有限公司,台北,1993。 52. http://www.valleydesign.com/pyrex.htm 53. P. P. Benham, Mechanics of Engineering Materials, Baker & Taylor Books, Essex, England, pp. 314, 1996. 54. O. V. Mazurin, M. V. Streltsina, T. P. S. Shvaikovskaya, Handbook of Glass Data, Elsevier, Amsterdam, Netherlands, 1983. 55. COMSOL Multiphysics Release v3.4, COMSOL, Inc., PA. 56. 洪東銘,內嵌穿晶片導線三維晶片模組之熱應力分析及最佳化,國立清華大學動力機械工程學系碩士論文,2008。
|