半導體製造技術不斷的演進，使得積體電路的電晶體數目，依舊遵循著摩爾定律成長。隨著電晶體的通道長度朝著物理極限不斷縮短，在電路的面積、速度和功率消耗上都有非常顯著的提升。然而，如此的情況僅局限於數位電路。對於類比電路而言，電路設計的技術將面臨更大的挑戰，例如：低電壓、低功率消耗的類比數位轉換器。

電子鼻 (Electronic Nose)是一種可以辨別氣體中特定的成分的裝置。電子鼻系統中需要使用類比數位轉換器作為前端感測器和數位信號處理器之間的橋樑。而低功率的消秏和低電壓操作是此類比數位轉換器最重要的議題。本論文提出一個應用於連續漸進式類比數位轉換器的軌對軌比較器，且操作電壓為1伏持並具有低功率消耗和低雜訊的特性。在電路設計上，使用電流鏡的技巧去克服輸出信號和輸入信號的相互干擾(kickback noise)。對於比較器的功率消耗方面，提出可適性功率控制電路來達到功率消耗的最佳化。一個連續漸進式類比數位轉換器於0.18製程，使用所提出之比較器和可適性功率控制電路，經實際量測試結果僅消耗2.86 μW，此時取樣頻率為250 kHz。FOM可達85.7 fJ/conversion-step。在可適產功率控制電路方面，它可以有效的降低比較器52%和80%的功率消耗，分別當取樣頻率為 125 kHz和500 kHz的時候。

The technology scaling down has provided much more gate count in silicon chips. The contraction of minimum channel length and decrease of power supply voltage have benefited digital circuits to smaller area, higher operation rate and lower power consumption. However, this progress of technology presents a number of challenges in mixed signal IC design.

In this thesis, a new 1V rail-to-rail comparator with low noise and low power consumption is presented. We utilize current mirrors to overcome the common issue, kickback noise. A new adaptive power control (APC) technique is also proposed to minimize the power dissipation of the comparator. Moreover, it provides an optimized and stable power dissipation irrelative to process and bias variation. A 1V rail-to-rail SAR ADC prototype, targets for biomedical applications, has been implemented in 0.18μm TSMC CMOS technology. It consumes 2.86 μW at 250kS/s and the figure of merit is 85.7 fJ/conversion-step. It shows that this work efficiently reduces 52% to 80% power consumption of the dynamic latched comparator at 500kS/s to 125kS/s.

Chapter 1 Introduction
1.1 Motivation
1.2 Architecture Selection
1.3 Thesis Organization
Chapter 2 Consideration of Circuit Design
2.1 MOS Switches
2.1.1 Channel Charge Injection
2.1.2 Clock Feedthrough
2.1.3 Transmission Gate
2.2 Mismatch of Device
Chapter 3 Architectures of SAR ADC
3.1 Global Architecture
3.2 Sample and Hold Circuit
3.2.1 Switch Bootstrapping
3.2.2 Bottom Plate Sampling
3.3 Latched Comparator
3.4 DAC Architecture
Chapter 4 Circuit Design
4.1 Conversion Plan
4.2 Comparator Circuit Design
4.3 Adaptive Power Control Circuit
4.4 DAC Circuit Design
4.5 SAR Circuit Design
Chapter 5 Measurement Result
5.1 Test Environment Setup
5.2 Characterization
5.3 Discussion
5.4 Summary
Chapter 6 Conclusion and Future Work

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