在本論文中，提出了一個具數位控制回授迴路的短通道可變增益放大器。為了節省面積，整體電路均使用最小通道長度的CMOS元件。此設計將導致電路產生嚴重的製程變異。為了解決這項問題，將需要兩個分別用來控制直流偏移校正以及增益校準的數位回授迴路。
此可變增益放大器採用具有衰減式電阻網路的全差動式增益級架構。藉由數位控制來改變電阻網路的阻值，以提供足夠的增益範圍與解析度。為了正確設定可變增益放大器的增益值，數位式的增益控制迴路必須在可變增益放大器操作之前啟動。直流偏移校正迴路則一直維持啟動狀態，用以防止輸出電壓飽和。藉由這兩個控制迴路，此可變增益放大器將不受製程變異的影響。
此量測晶片採用台積電0.18-μm 1P6M互補式金屬半導體氧化物製程，面積共佔292 μm × 592 μm。此可變增益放大器可提供-3.9 ~ 48.3 dB的增益範圍，在增益間距為6-dB的前提下，實際量測所得增益值和理想值之間的誤差值小於0.5 dB。在最大增益的設定下，頻寬為10.85 MHz。在輸出訊號為10-MHz，輸出擺幅為400-mVppd的情形下，總諧波失真 (THD) 在最大和最小的增益設定下分別為 -33.82 dB 和 -48.08 dB。當輸入的直流偏移電壓在-70 ~ +50 mV的範圍內時，輸出的偏移電壓小於20 mV。在1.8-V電壓供應的前提下，此晶片消耗12.1 mA的電流。

In this thesis, a short-channel variable gain amplifier with digital feedback loops is proposed. For the purpose of area saving, the entire work is implemented with minimum gate length CMOS devices. This results in severe circuit process variations. To overcome this problem, two digital feedback loops are needed for the DC offset cancellation and gain calibration.
The VGA circuit is based on a fully-differential gain stage with a degeneration resistor network. The resistance of this resistor network is digitally controlled to provide enough gain range and resolution. To properly set the VGA gain, the digital gain calibration loop is enabled before the VGA operates. The DC offset cancellation loop is always active to prevent the VGA output from DC saturation. With the aid of both loops, the proposed VGA is robust against process variations.
An experimental chip is fabricated in TSMC 0.18-μm 1P6M CMOS process. The core area occupies 292 μm × 592 μm. The available gain range of the VGA is -3.9 ~ 48.3 dB. For a 6-dB gain step requirement, the gain error is less than 0.5 dB. The bandwidth at the maximum gain setting is 10.85 MHz. With 10-MHz 400-mVppd sinusoidal output waveform, the total harmonic distortion (THD) at maximum and minimum gain setting are -33.82 dB and -48.08 dB respectively. The output DC offset voltage is less than 20 mV when the input DC offset voltage is within -70 ~ +50 mV. The current consumption from a single 1.8-V power supply is 12.1 mA.

List of Figures
List of Tables

Chapter 1: Introduction
1.1 Motivation
1.2 Receiver Architecture
1.3 Thesis Organization

Chapter 2: Architecture of the Short-Channel VGA
2.1 VGA Overview
2.1.1 VGA Fundamental
2.1.2 Linear-in-dB Gain Control
2.2 The Proposed Short-Channel VGA Architecture
2.2.1 VGA Gain Stages
2.2.2 DC Offset Cancellation Loop
2.2.3 Gain Calibtation Loop
2.3 Summary

Chapter 3: Design of the Short-Channel VGA Gain Stages
3.1 Overview
3.2 VGA Cell
3.3 MOS Resistor Network
3.4 Common Mode Feedback
3.5 Output Buffer
3.6 Bias Circuit
3.7 Simulation Results
3.8 Summary

Chapter 4: Design of the DC Offset Cancellation Loop
4.1 Overview
4.2 Operation of the DC Offset Cancellation Loop
4.2.1 Successive Approximation Register (SAR) Cancellation Path
4.2.2 Accumulator (ACC) Cancellation Path
4.3 Circuit Blocks
4.3.1 Comparator
4.3.2 Successive Approximation Register (SAR) Controller
4.3.3 Accumulator (ACC)
4.3.4 DAC
4.4 Simulation Results
4.5 Summary

Chapter 5: Design of the Gain Calibration Loop
5.1 Overview
5.2 Operation of the Gain Calibration Loop
5.3 Circuit Blocks
5.3.1 Fully-Differential S/H
5.3.2 Comparator
5.3.3 Successive Approximation Register (SAR) Controller
5.4 Simulation Results
5.5 Summary

Chapter 6: The Short-Channel VGA System Simulation and Measurement Results
6.1 Mixed-Mode Circuit Simulation
6.1.1 System Operation
6.1.2 Simulation Results
6.2 Chip Measurement
6.2.1 Measurement Setup
6.2.2 Measurement Results
6.3 Summary

Chapter 7: Conclusion and Future Works

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