現今的系統單晶片中，靜態隨機存取記憶體往往占據最大的面積，也因此靜態隨機存取記憶體往往是系統單晶片降低功率消耗的瓶頸。有鑑於此，若能夠使靜態隨機存取記憶體操作在低供應電壓下，其功率消耗便能有效的降低。但由於傳統的六電晶體式之靜態隨機存取記憶單元，受限於本身的架構，在低電壓下往往容易發生讀取以及寫入上的錯誤，以致於傳統的靜態隨機存取記憶體的在供應電壓降低時很容易出現錯誤位元，而此種情況先進製程更甚。而在低電壓操作之下，由於電晶體自身的驅動能力減弱，因此在低電壓下靜態隨機存取記憶體往往達不到高操作速度。
有鑑於此，本篇論文中，吾等提出一新型態之十個電晶體架構之記憶單元，該單元是由利用與寫入資料相關的差動操作電壓的特性，並由字元線供給記憶單元操作電壓的架構，大幅幫助寫入的成功率以及速度[57, 75]。除此之外，一個由二個電晶體構成的獨立讀取路徑，可使得記憶單元在讀取時能夠達到無讀取干擾的同時也能夠在速度上有顯著的提升。我們除了以此新型態的靜態隨機存取記憶體為記憶單元之外，也使用了一些架構上的設計技巧，如分割字組線以及複製字元線等，使得記憶體電路得以在低電壓之下操作具有更佳的穩定性。在整個靜態隨機存取記憶體電路設計中，我們也使用了一些針對低電壓操作速度的提升方式，像是減少傳輸閘的使用數量、對列解碼路徑上關鍵的P型電晶體，施以基底順向偏壓提升其驅動能力，以及一高速的感測電路，可使讀取資料零的效能被進一步的提升[91]。
最後我們已提出的十電晶體記憶單元搭配前述的技巧，以九十奈米互補式金氧半製程技術，建構出一個由一十六千字元(16Kb)組成的靜態隨機存取記憶體電路。量測結果顯示以此種十電晶體之靜態隨機存取記憶體為記憶單元的電路，在供應電壓為四百五十毫伏下，操作頻率可達三百百萬赫茲。且整個電路可達到的最低 操作電壓為二百二十毫伏。

Contents
Abstract (Chinese)
Abstract (English)
Acknowledgments (Chinese)
Contents ................................................i
List of Figures ................................................iv
List of Tables ................................................xii

Chapter1 Introduction ...................................1
1.1 Background ..........................................1
1.2 Challenges of Low-Voltage SRAM ......................5
1.3 Motivation ..........................................5
1.4 Thesis Structure ....................................6
Chapter2 Design Issues of Low Voltage SRAM ..............7
2.1 Analyses of Conventional 6T SRAM cell ...............8
2.1.1 Static Noise Margin (SNM) ........................10
2.1.2 Write Margin (WM) ................................13
2.2 Difficulties of 6T SRAM at Low VDD .................15
2.2.1 Device Variability ...............................15
2.2.2 Read Stability Degradation and Read Failure.......16
2.2.3 Write Ability Degradation and Write Failure ......18
2.3 Previous Solutions .................................19
2.3.1 Function Enhanced Techniques for 6T SRAM .........20
2.3.2 Novel Bitcell Structures .........................22

Chapter3 Basic Operations of Proposed 10T SRAM Bitcell..28
3.1 Structure of Proposed 10T Bitcell ..................28
3.2 Standby Mode .......................................29
3.3 Read Operation .....................................31
3.4 Write Operation ....................................35
3.4.1 Basic Write Operation ............................36
3.4.2 Power Floating Issue .............................38
3.4.3 Half-Select Disturb Problem ......................39

Chapter4 Analyses of Proposed 10T SRAM cell .............42
4.1 Differential Power-supplied Write Assist............ 42
4.2 Disturb-Free Read Access ............................46
4.3 Analyses for Power Floating Condition ...............48
4.4 Power Consumption Analysis...........................51
4.5 Layout Considerations ...............................53
4.6 Comparisons Between 10T cell in this work and D2AP 8T cell ....................................................55

Chapter5 Proposed SRAM Macro Implementation .............63
5.1 Architecture of Conventional SRAM Macro .............63
5.2 Architecture of Proposed SRAM Macro .................65
5.2.1 Divided Word Line (DWL) Structure .................66
5.2.2 Divided Bit Line (DBL) Structure ..................69
5.2.3 Self-Timing Control Scheme ........................72
5.2.4 Proposed 10T SRAM Macro ...........................74
5.3 Test Chip Design ....................................80

Chapter6 Experimental Results and Conclusions ...........82
6.1 Measurement Results .................................82
6.2 Summary and Conclusion of this Thesis ...............88
6.3 Future Works ........................................92

References ..............................................94

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