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作者(中文):吳宜軒
作者(外文):Wu, Yi-Shiuan
論文名稱(中文):利用基體偏壓之0.5 伏特高斯頻移鍵控解調器
論文名稱(外文):A 0.5V GFSK Demodulator with Body-Bias Technique
指導教授(中文):黃柏鈞
指導教授(外文):Huang, Po-Chiun
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學號:9661587
出版年(民國):99
畢業學年度:98
語文別:英文
論文頁數:57
中文關鍵詞:藍芽高斯頻移鍵控解調器0.5伏特基體輸入
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由於手持式無線通訊電子產品需求量的增加,為了延長電子產品使用的時間,最直接的方式就是降低操作電壓,使系統達到低功率消耗。而且為了減少電池在電子產品中所占的體積和重量,太陽能將成為另一種提供能源的方式,由於太陽能電池所能供應的電壓約為0.5伏特,因此我們以藍芽( Bluetooth )做為參考規範,設計一個操作在0.5伏特高斯頻移鍵控( GFSK )的解調器。
在這個研究當中包含了兩個部分,一個是將訊號拉到軌對軌( rail to rail )的限幅放大器( Limiting Amplifier ),另一個則是用延遲鎖相迴路為架構的解調器。限幅放大器主要的目地是提供足夠的增益,讓類比的信號轉換成數位信號,為了避免電路本身的雜訊影響訊號,也會對這一個部分進行分析。而解調方面則是將拉到軌對軌的數位信號延遲一段固定的時間,之後將延遲的信號對原來的信號去做取樣,藉由判斷相位的超前和落後,來達到解調的目的。而延遲鎖相迴路( DLL )就是利用回授的方式準確的鎖定我們所需要的延遲時間( 1/3MHz )。
由於大部分電路都是偏數位方面的電路,比較適合操作在較低的工作電壓,此外,數位電路並不消耗直流電流,可以進一步減低功率的消耗。晶片的製作採用台積電0.18um 1P6M 製程來實現,晶片面積為1.54mm2,在此設計當中,選擇以3 MHz作為居中頻率( Intermediate Frequency, IF ),在0.5伏特的操作電壓下,功率消耗為0.2mW。
1 Introduction 1
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Test Circuit for Bulk Input Structure 3
2.1 Low Voltage Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Simulation and Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 FSK Receiver Architecture 11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Receiver Radio Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 Heterodyne Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2 Homodyne Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.3 Low-IF Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 System Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Limiting Amplifier 21
4.1 Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.1 Gain Stage Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.2 Offset Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.3 Common Mode Feedback . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1.4 Noise Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5 FSK Demodulator 33
5.1 FSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.1 Differentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.2 PLL type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.3 Quadrature Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.4 Zero-crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2.5 DLL type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3 DLL type FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.1 Phase Frequency Detector . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.2 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.3 Voltage Controlled Delay Line . . . . . . . . . . . . . . . . . . . . . . 45
5.3.4 LO Shift Compensation . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.4 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6 Measurement Result 50
6.1 Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.1 SNR to BER Measurement . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.2 Noise of the Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.3 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7 Conclusion 56
7.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
[1] M. Trakimas and S. Sonkusale, “A 0.5 V bulk-input operational transconductance ampli-
fier with improved common-mode feedback,” in IEEE International Symposium on Cir-
cuits and Systems (ISCAS), May 2007, pp. 2224–2227.
[2] A.-A. Abidi, “Direct-conversion radio transceivers for digital communications,” IEEE
Journal of Solid-State Circuits, vol. 30, no. 12, pp. 1399–1410, Dec. 1995.
[3] J. Crols and M. Steyaert, “Low-IF topologies for high-performance analog front ends of
fully integrated receivers,” IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing, vol. 45, no. 3, pp. 269–282, Mar. 1998.
[4] S. Samadian, R. Hayashi, and A.-A. Abidi, “Demodulators for a zero-IF Bluetooth re-
ceiver,” IEEE Journal of Solid-State Circuits, vol. 38, no. 8, pp. 1393–1396, Aug. 2003.
[5] P.-C. Huang, Y.-H. Chen, and C.-K. Wang, “A 2-V 10.7-MHz CMOS limiting ampli-
fier/rssi,” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1474–1480, Oct. 2000.
[6] E. Klumperink, C. Klein, B. Ruggeberg, and E. van Tuijl, “AM suppression with low
AM-PM conversion with the aid of a variable-gain amplifier,” IEEE Journal of Solid-State
Circuits, vol. 31, no. 5, pp. 625–633, May 1996.
[7] S. Chatterjee, Y. Tsividis, and P. Kinget, “0.5-V analog circuit techniques and their appli-
cation in OTA and filter design,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp.
2373–2387, Dec. 2005.
[8] P.-C. Huang, Y.-H. Chen, and C.-K. Wang, “A 2-V CMOS 455-kHz FM/FSK demodula-
tor using feedforward offset cancellation limiting amplifier,” IEEE Journal of Solid-State
Circuits, vol. 36, no. 1, pp. 135–138, Jan. 2001.
[9] Y.-C. Chen, Y.-C. Wu, and P.-C. Huang, “A 1.2-V CMOS limiter / RSSI / demodulator
for low-IF FSK receiver,” in IEEE Custom Integrated Circuits Conference (CICC), Sep.
2007, pp. 217–220.
[10] B. Blalock, P. Allen, and G. Rincon-Mora, “Designing 1-V op amps using standard digital
CMOS technology,” IEEE Transactions on Circuits and Systems II: Analog and Digital
Signal Processing, vol. 45, no. 7, pp. 769–780, July 1998.
[11] Y. Moon, J. Choi, K. Lee, D.-K. Jeong, and M.-K. Kim, “An all-analog multiphase delay-
locked loop using a replica delay line for wide-range operation and low-jitter perfor-
mance,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 377–384, Mar. 2000.
[12] H.-H. Chang, J.-W. Lin, C.-Y. Yang, and S.-I. Liu, “A wide-range delay-locked loop with
a fixed latency of one clock cycle,” IEEE Journal of Solid-State Circuits, vol. 37, no. 8,
pp. 1021–1027, Aug. 2002.
[13] H.-H. Hsieh, C.-T. Lu, and L.-H. Lu, “A 0.5-V 1.9-GHz low-power phase-locked loop in
0.18-m CMOS,” in IEEE Symposium on VLSI Circuits, June 2007, pp. 164–165.
[14] T. Matsumoto, “High-resolution on-chip propagation delay detector for measuring within-
chip variation,” in International Conference on Integrated Circuit Design and Technology
(ICICDT), May 2005, pp. 217–220.
[15] H.-H. Chang, C.-H. Sun, and S.-I. Liu, “Low jitter Butterworth delay-locked loops,” in
Symposium on VLSI Circuits. Digest of Technical Papers., June 2003, pp. 177–180.
[16] H. Darabi, S. Khorram, B. Ibrahim, M. Rofougaran, and A. Rofougaran, “An IF FSK
demodulator for Bluetooth in 0.35 um CMOS,” in IEEE Custom Integrated Circuits Con-
ference (CICC), Dec. 2001, pp. 523–526.
[17] S. Byun, C.-H. Park, Y. Song, S. Wang, C. Conroy, and B. Kim, “A low-power CMOS
Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator,”
IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1609–1618, Oct. 2003.
[18] B. Xia, C. Xin, W. Sheng, A. Valero-Lopez, and E. Sanchez-Sinencio, “A GFSK demod-
ulator for low-IF Bluetooth receiver,” IEEE Journal of Solid-State Circuits, vol. 38, no. 8,
pp. 1397–1400, Aug. 2003.
[19] H.-S. Kao, M.-J. Yang, and T.-C. Lee, “A delay-line-based GFSK demodulator for low-IF
receivers,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2007, pp.
588–589.
[20] L.-S. Lai, H.-H. Hsieh, P.-S. Weng, and L.-H. Lu, “An experimental ultra-low-voltage de-
modulator in 0.18-m CMOS,” IEEE Transactions on Microwave Theory and Techniques
(MTT), vol. 57, no. 10, pp. 2307–2317, Oct. 2009.
 
 
 
 
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