近年來在ＩＣ設計時，功率成為一個很重要的考量，愈來愈多低功率的設計技術不斷的被發展出來。在數位電路的系統裡，藉由適當的電壓調變，可以有效的達成低功率消耗的目的，主要是因為提供了較低的操作電壓。這篇論文著重於在電壓調變下的數位電路操作，更進一步探討將操作電壓降低至電晶體的次臨界區中所產生的現象。我們所遭遇到的一些問題不僅僅是低功率設計所會面對到的，由於操作電壓不斷下降至愈來愈接近臨界電壓，這些現象也可能在先進的製程裡看到。
當提供不同的操作電壓時，電路的特性會產生很大的變化，在一般操作電壓的設計準則無法保證在低電壓時依然可以使電路得到最佳化的效果。我們會提供一個方法來解決P型半導體和N型半導體在電壓調降時所產生的不匹配效應，使得電路比較不受電壓調變所影響，這個方法可以被拿來用在動態電壓頻率調變系統中；此外我們也對一些常用的數位電路元件作一些檢測，確保他們在低電壓時能正確地運作，像是序向電路、傳輸閘邏輯、其它的邏輯組合電路等；我們也對於在低電壓時的電路架構設計做了一些討論，主要是確保他們能保持在最佳化的設計。

In recent years, power has become one of the most important issues for chip designs. A lot of low-power design techniques have been developed. In digital circuits, adaptive voltage scaling is an effective approach to achieve low power design due to its lower supply voltage. This thesis focuses on the digital circuit operation while the power supply voltage is scaled down even to the sub-threshold region of the MOS transistor. The issues we encountered may happen not only in low power design but also become common issues while the supply voltage scaling down to close the threshold voltage in advanced technologies.
With different (lower) supply voltage, the characteristic of circuit would be changed significantly. The design guidelines in nominal supply voltage cannot guarantee optimumality in low supply voltage. We are going to fix the performance degradation due to threshold voltage mismatch of PMOS and NMOS when voltage is scaled down. Develop a feasible solution to design a voltage insensitive digital circuit. It can be used in DVFS (Dynamic Voltage Frequency Scaling) system. Then we check the functionality of common used cell in digital circuits such as sequential cells, transmission gates, and other logic cells. Moreover, we’ll take a look at the circuit architecture to ensure the circuit not to deviate the optimal point too far.

Chapter 1 Introduction
1.1 Background
1.2 Motivation
1.3 Organization
Chapter 2 Votlage Scaling in Digital Circuit
2.1 Sub-threshold Region
2.2 Case Study - Circuit in Low Supply Voltage
2.3 Discussions
Chapter 3 Threshold Voltage Matching
3.1 Proposed Solutions
3.2 Formulation
3.3 Simulation Result
Chapter 4 Design Consideration with Voltage Scaling
4.1 Process Variation
4.2 Energy Efficiency
Chapter 5 Impacts on Circuit Structure
5.1 Ratio Design
5.2 Transistor Connection
5.3 Other Logic Family
5.4 Sequential Circuit
Chapter 6 Conclusion
6.1 Conclusion
6.2 Future Work

[1] M. Anis, "Sub-threshold leakage current: challenges and solutions," Proceedings of the 15th International Conference on Microelectronics 2003, pp.77-80, 9-11 Dec. 2003

[2] T. Burd, T. Pering, A. Stratakos, R. Brodersen, "A dynamic voltage scaled microprocessor system," IEEE International Solid-State Circuits Conference 2000. Digest of Technical Papers, pp.294-295, 466, 2000

[3] B.H. Calhoun, A. Wang, A. Chandrakasan, "Modeling and sizing for minimum energy operation in sub-threshold circuits," IEEE Journal of Solid-State Circuits, vol.40, no.9, pp. 1778-1786, Sept. 2005

[4] Ramesh Vaddi, S. Dasgupta, R. P. Agarwal, “Device and Circuit Design Challenges in the Digital Sub-threshold Region for Ultralow-Power Applications,” VLSI Design, pp.1-14, 2009

[5] ITC’99 benchmark circuit
URL: http://www.cerc.utexas.edu/itc99-benchmarks/bench.html

[6] J. Keane, Hanyong Eom; Tae-Hyoung Kim, S. Sapatnekar, C. Kim, "Stack Sizing for Optimal Current Drivability in Sub-threshold Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, no.5, pp.598-602, May 2008

[7] H.P. Alstad, S. Aunet, "Seven sub-threshold flip-flop cells," Norchip, 2007, pp.1-4, 19-20 Nov. 2007

[8] Wai Chung, T. Lo, M. Sachdev, "A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.10, no.6, pp. 913-918, Dec 2002

[9] V. Stojanovic, V.G. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," IEEE Journal of Solid-State Circuits, vol.34, no.4, pp.536-548, Apr 1999

[10] E.P. Vandamme, P. Jansen, L. Deferm, "Modeling the sub-threshold swing in MOSFET's," IEEE Electron Device Letters, vol.18, no.8, pp.369-371, Aug 1997
[11] A. Wang, A. Chandrakasan, "A 180mV FFT processor using sub-threshold circuit techniques," IEEE International Solid-State Circuits Conference 2004. Digest of Technical Papers, pp. 292-529 Vol.1, 15-19 Feb. 2004

[12] B.H. Calhoun, A. Chandrakasan, "Characterizing and modeling minimum energy operation for sub-threshold circuits," Proceedings of the 2004 International Symposium on Low Power Electronics and Design, pp. 90-95, 9-11 Aug. 2004

[13] H. Soeleman, K. Roy, B. Paul, "Sub-Domino logic: ultra-low power dynamic sub-threshold digital logic," Fourteenth International Conference on VLSI Design 2001, pp.211-214, 2001

[14] H. Soeleman, K. Roy, B.C. Paul, "Robust sub-threshold logic for ultra-low power operation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.9, no.1, pp.90-99, Feb 2001

[15] B.C. Paul, H. Soeleman, K. Roy, "An 8×8 sub-threshold digital CMOS carry save array multiplier," Proceedings of the 27th European Solid-State Circuits Conference 2001, pp. 377-380, 18-20 Sept. 2001

[16] M. Elgebaly, M. Sachdev, "Efficient adaptive voltage scaling system through on-chip critical path emulation," Proceedings of the 2004 International Symposium on Low Power Electronics and Design 2004, pp. 375-380, 9-11 Aug. 2004

[17] M. Elgebaly, M. Sachdev, "Variation-Aware Adaptive Voltage Scaling System," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.15, no.5, pp.560-571, May 2007

[18] H. Ananthan, C.H. Kim, K. Roy, "Larger-than-Vdd Forward Body Bias in Sub-0.5V Nanoscale CMOS," Proceedings of the 2004 International Symposium on Low Power Electronics and Design, pp. 8-13, 2004

[19] N. Verma, J. Kwong, A.P. Chandrakasan, "Nanometer MOSFET Variation in Minimum Energy Sub-threshold Circuits," IEEE Transactions on Electron Devices, vol.55, no.1, pp.163-174, Jan. 2008

[20] V. Eisele, B. Hoppe, O. Kiehl, "Transmission gate delay models for circuit optimization," Proceedings of the European Design Automation Conference 1990, pp.558-562, 12-15 Mar 1990

[21] Bo Fu, P. Ampadu, "Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency," IEEE International Symposium on Circuits and Systems 2007, pp.1173-1176, 27-30 May 2007

[22] V. Moalemi, A. Afzali-Kusha, "Sub-threshold Pass Transistor Logic for Ultra-Low Power Operation," IEEE Computer Society Annual Symposium on VLSI 2007, pp.490-491, 9-11 March 2007

[23] N. Weste and D. Harris, “Circuit Simulation,” in CMOS VLSI Design, A Circuit
and System Perspective, 3rd ed., Addison-Wesley Longman Publishing Co., Inc..,
2004, ch2,ch6,ch7,ch10.

[24] J. Kwong, A.P. Chandrakasan, "Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits," Proceedings of the 2006 International Symposium on Low Power Electronics and Design 2006, pp.8-13, 4-6 Oct. 2006

[25] Hendrawan Soeleman, Kaushik Roy, “Digital CMOS logic operation in the sub-threshold region,” Proceedings of the 10th Great Lakes symposium on VLSI, pp.107-112, March 02-04 2000.