本論文針對H.264高等影像編碼技術提出一個高效能以及低功率的去區塊效應濾波器之硬體架構。 根據濾波器本身之特性，我們採用了五階層管線化架構以增進系統效能並達到降低功率耗損的目標。 在此設計中會產生兩種管線化危機，其包含資料危機以及結構危機，我們採用了資料前送機制以及進階的記憶體架構來解除這兩種危機。 在使用了混雜式的濾波流程以及大區塊層級的管線化技術之後，平均上只要需要198個時脈週期就能夠處理完一個大區塊，而這也是一個將近最佳化的速度。 我們的設計能夠在200百萬赫茲的時脈上運作而這是一般非管線化設計的去區塊效應濾波器所不能達到的。 此外，在使用了時脈閘控、記憶體存取次數化簡、記憶體元件縮減、以及計算元件縮減之後，我們的設計只有144微瓦的功率耗損。 以上的功率實驗是將我們的設計運作在600千赫茲的時脈上以及1伏特的電壓供應，而受測驗的影片規格是QCIF每秒鐘播放30張圖片。 與現今最好的設計比較起來，我們的設計能夠達到至少3%的的效能增進以及降低至少17%的功率耗損。
This thesis proposes a low-power and high-performance deblocking filter architecture for H.264/AVC. Based on the feature of filtering operation, a five-stage pipeline architecture is adopted in the hardware to increase the system throughput while reducing the power consumption. Data hazards and structure hazards, the two main hazards in our pipeline design, are analyzed and solved by data forwarding and improved memory architectures respectively. With the proposed hybrid edge filter order and macroblock-level pipeline technique, only 198 cycles on average, the near optimal performance, are needed to filter one macroblock. Our design can be operated at 200 MHz clock rate which cannot be achieved by non-pipeline architectures proposed by previous designs. Moreover, by using clock gating, memory access reduction, memory device reduction, and calculation element reduction, it consumes only 144 μw when running at 600 KHz clock rate for QCIF 30 fps with 1 V power supply. Compared with the best designs available, our design achieves at least not only 3% processing cycle reduction, but also 17% power consumption reduction.

中文摘要 II
Abstract III
Contents IV
List of Figures V
List of Tables VI
Chapter 1 Introduction 1
Chapter 2 Related Work 5
Chapter 3 Deblocking Filter Algorithm 7
3.1 Boundary Strength 9
3.2 Threshold Values 10
3.3 Filtering Computations 11
Chapter 4 Proposed Hardware Architecture 13
4.1 Deblocking Filter Architecture 13
4.2 Edge Filter Order Analysis 14
4.2.1 Literature Edge Filter Order Evaluation 15
4.2.2 Proposed Edge Filter Order 16
4.3 Proposed Pipeline Architecture 17
4.3.1 Five-stage Pipeline Filter Engine and MB-level pipeline 17
4.3.2 Pipeline Hazards 21
4.4 Local Memory Organization 24
4.5 Edge Filtering Process 28
4.6 Low-power Techniques 30
4.6.1 System Clock Gating 30
4.6.2 Pipeline Clock Gating 31
4.6.3 Other Approaches 32
Chapter 5 Experimental Result 34
5.1 Performance Comparisons 36
5.2 Hardware Cost Comparisons 38
5.3 Power Analysis 39
Chapter 6 Conclusion and Future Work 41
Reference 43

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