As IC design entering deep sub-micron age, rapidly progress of advanced process technology
allows higher integration density of a single chip. This enables SoC (System-on-Chip) to
become viable. SoC can integrate a large variety of heterogeneous cores, but it also brings
testing challenges. The complex functions in SoC make testing even more difficult than
before. Besides, traditional ATE (automatic test equipment) is becoming harder to catch up
with the growing fabrication technology, such as increasing IO pins, more timing accuracy
requirement, and higher clock frequency. A wireless testing system, HOY [1], is proposed to
cope with the coming challenges. Removing the traditional contact probing mechanism, HOY
system demands a pair of transceiver to transmit/receive command and data wirelessly and
test DUT (device under test) with embedded BIST (Built-In Self-Test). With HOY wireless
testing system, the limitation in traditional ATE will be resolved eventually.
To enable wireless communication in practical system, a one-on-one MAC protocol had
been made. However, for parallelism, the overall system performance will suffer from frequent
context-switching of multi-threading. Consequently, a next-generation multicast protocol
had been proposed in [2], and the corresponding implementation in ESL (Electronic System
Level) has been made in [3]. Based on the previous work, we formulate time cost function
of the multicast protocol with crucial parameters of the protocol. We also analyze the
cost function under different bit error rates and amount of total DUTs. We find that the
two parameters, bit error rate and number of DUTs, have exponential impact on system
performance. Thus, we propose a grouping approach to allow trade-off between bit error
rate and amount of groups. This approach extends distances among DUTs in a single group
and reduces bit error rate, but meanwhile, it also increases time cost in MD (multicast data)
stage among different groups. After applying this method, the testing time under multicast protocol grows linearly with amount of DUTs instead of the original exponential growth.
In addition, to estimate communication quality of practical HOY prototype, we modify
MAC (media access control) module in the original HOY system. With the consideration
of enhancing measurement efficiency and eliminating uncertainty, we embedded PRPG
(Pseudo-Random Pattern Generator) and controller in both ATE and DUT to handle the
BER (bit error rate) measurement. Also we integrate the BER testing flow of the overall
system for both the MAC layer and RF layer with unified procedure. Furthermore, we verify
our design by using FPGA, RF module and test chips. The measurement result shows that
the BER is less than 10−6 in realistic HOY system prototype.

隨著積體電路製桯的快速演進，晶片裡單位面積所能包含的電路數量愈來愈多，要達成SoC (System-on-Chip) 變得輕而易舉。雖然SoC能整合許多不同的core在一顆chip內，同時卻也帶來許多在測試上的問題。SoC的功能變得更複雜，傳統測試機台 (ATE) 很難跟上SoC發展的腳步，諸如pin腳的數量愈來愈多、timing準確性的要求愈來愈高、亦或是clock的工作時脈愈來愈快等，都會造成測試上的困難。於是，HOY這個概念被提出以克服上述的問題。HOY是個無線測試的系統，它拋棄了舊有接觸惑的探針卡 (probe card) 機制，而改用一組transceiver來作為資料溝通的介面，並且在測試方法是透過內建自我測試 (Built-In Self-Test, BIST) 的模組來達成。在HOY無線測試系統下，將能突破傳統測試機台的瓶頸限制。
在先前的計畫，已建立了實際的HOY無線測試系統來驗證HOY的概念；然而，在目前的系統下要達成平行測試，整體效能將受限於軟體的多執行緒的內文切換 (context-switching)。為了解決這個問題，下一代的多工通訊協定已被提出，並在系統層級的模型上建構並得到驗證。基於該模型，我們對它做了時間成本的函式建構，找出及參數化此模型中最關鍵的幾個變數。我們發現位元錯誤率及待測電路的數量是整個測試時間的最關鍵變數，接著我們在不同的位元錯誤率及不同數量的待測電路下對該函式進行分析，結果顯示這兩個變數對整個系統的測試時間有指數性的影響。於是我們提出一個群組化的方法來降低這兩個參數對測試時間的影響，該方法允許時間函式在位元錯誤率與群組數量間做權衡，但同時也要付出額外的時間在多播 (multicast data)的階段。在套用該方法後，測試時間與DUT數量的關係將呈現現性成長而非原來的指數成長。
　　此外，在實際的HOY系統下，我們對MAC模組進行了修改，使其能支援整個系統的位元錯誤率的量測。在考量整體效能與排除測試的不確定性後，我們在MAC裡加入了PRPG (Pseudo-Random Pattern Generator)及其控制元件在ATE及DUT端以控制整個位元錯誤率量測的流程。另外，我們也在FPGA上與HOY0803的射頻模組共同驗證了我們的設計，並且量測到在系統層級的位元錯誤率在10-6以下。

1 Introduction 1
1.1 Traditional Testing Background and Issue . . . . . . . . . . . . . . . . . . . 1
1.2 HOY System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 Hypothesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.2 Odyssey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.3 Yield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 System Design in Electronic System Level (ESL) . . . . . . . . . . . . . . . . 5
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Related Works 7
2.1 HOY Prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Multicast MAC Protocol Design in Electronic System Level . . . . . . . . . . 9
2.3 Related Work about Wireless Testing . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Related Work about Multicast Protocol . . . . . . . . . . . . . . . . . . . . . 13
3 Time Cost Modeling 15
3.1 Introduction to SystemC Modeling of HOY Multicast MAC Protocol . . . . 15
3.2 Time Cost Formulation for HOY Multicast MAC Protocol . . . . . . . . . . 16
ii
3.2.1 Time Cost in TI Stage . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 Time Cost in MD Stage . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.3 Time Cost in PL Stage . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Time Cost Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.1 Time Intensive Transmission . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.2 Data Intensive Transmission . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.1 Scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.2 Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.3 Results Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Design for Bit Error Rate Measurement 29
4.1 Features for BER Measurement . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.1 Isolating BER Measurement from Original Core Test . . . . . . . . . 30
4.1.2 Separating BER Measurement Flow into Up/Down-link . . . . . . . . 30
4.1.3 Disabling Test Modules . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.4 Eliminating Frame Header Triggering Mechanism . . . . . . . . . . . 31
4.1.5 Inactivating CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 Bit Error Rate Measurement Flow . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.2 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2.3 BER Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2.4 Result Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
iii
4.2.4.1 Downlink BER Result Collection . . . . . . . . . . . . . . . 40
4.2.4.2 Uplink BER Result Collection . . . . . . . . . . . . . . . . . 41
4.2.5 BER Measurement Summary . . . . . . . . . . . . . . . . . . . . . . 42
4.3 Implementation for BER Measurement . . . . . . . . . . . . . . . . . . . . . 43
4.4 Experimental Result and Analysis . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4.1 Experiment Environment and Setup . . . . . . . . . . . . . . . . . . . 47
4.4.1.1 2nd Version of Test Chip . . . . . . . . . . . . . . . . . . . . 47
4.4.1.2 FPGAs for BER Measurement . . . . . . . . . . . . . . . . 48
4.4.2 Experiment Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4.3 Experimental Result . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5 Conclusion and Future Work 55
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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