過去五十年來，隨著摩爾定律的預測，積體電路上的電晶體數量約每兩年就成長一倍，業界也跟隨著 ITRS (International Technology Roadmap for Semiconductors)技術藍圖到達每個電子新技術世代，而以無機半導體作為基底材料的製程發展，造就了現在的電子科技榮景。我們追求三大目標：更小，更快，更冷。更小指的是元件的尺寸更小；更快指的是更快的操作速度；更冷指的是更小的功率損耗。在微縮電晶體同時，也追求更高的電路操作速度和可靠度。為提高運算性能，我們不停的提高電晶體集成度，但近年來，我們在縮小尺寸上遇上了較多的困難，科學家們根據摩爾定律預測，無機半導體積體電路的發展，將在 2020 年左右達到極限。但若想更進一步的提高集成度，各個期刊提出分子電子相關討論。這類研究提供了一個方向去延伸摩爾定律並克服已預見的微縮限制。我們可以預估，20 世紀是無機半導體的世紀，21 世紀將是有機分子電子學的世紀。

本篇論文的內容是先以奈米線遮罩法做出 10 nm 上下的奈米狹縫，此奈米狹縫非常筆直，且寬度一致，以這樣特性的奈米狹縫電極，可提供研究分子電子學一個良好的基礎。再利用熱蒸鍍法，將碳 60 分子沉積在奈米狹縫中，形成超短通道碳 60 電晶體。

本篇第一章介紹分子電子學與碳家族的特性。第二章討論現今製作奈米狹縫的各種技術。第三章分享製作超短通道碳 60 電晶體的方法，包含如何泡製奈米線溶液，並將其均勻的分布於樣品表面，利用定位系統準確的選擇奈米線遮罩，並連接電極，最後沉積碳 60 即可成功地得到超短通道碳 60 電晶體。

摘要 i
致謝 ii
1 緒論
1.1 分子電子學 1
1.2 碳家族 3
1.3 富勒烯-碳 60（Fullerene-C60） 9
2 奈米級元件與技術
2.1 導論 16
2.2 製作奈米狹縫之技術 17
2.2.1 機械力學折斷法（Mechanically controlled break junction, MCBJ） 17
2.2.2 電化學電鍍法（Electrochemical plating） 19
2.2.3 電子束微影法（Electron-beam lithography） 20
2.2.4 電致遷移法（Electromigration） 21
2.2.5 線上微影法（On-wire lithography, OWL） 23
2.2.6 雙角度蒸度法（Double-angle evaporation） 24
2.2.7 遮罩法（Shadow mask method） 26
3 元件製程
3.1 引言 28
3.2 微影技術 28
3.2.1 光學微影技術（Optical lithography） 29
3.2.2 電子束微影技術（Electron-beam lithography） 29
3.3 奈米線溶液製備 30
3.4 元件結構 31
3.5 奈米狹縫製作流程 32
3.5.1 試片準備 34
3.5.2 旋塗下層電子阻 35
3.5.3 沉積五氧化二釩奈米線 35
3.5.4 定義奈米狹縫區域 37
3.5.5 旋塗下層電子阻 38
3.5.6 電子束微影 38
3.5.7 金屬蒸鍍 39
3.6 金線連接術 41
3.7 沉積碳 60 41
4 結構分析與電性量測
4.1 奈米狹縫結構分析 43
4.1.1 分析儀器 44
4.1.2 懸浮奈米線之SEM分析 48
4.1.3 元件分析 51
4.2 製作奈米狹縫元件遭遇之問題 54
4.2.1 對準問題 54
4.2.2 電子束微影 55
4.2.3 電極厚度問題 55
4.3 電性量測 56
4.3.1 量測結果分析 57
5 結論與展望 62
Reference 63

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