仿神經系統之中，儲存類比値參數於懸浮閘內，可以使系統不經數位類比轉換，執行大量之平行運算；但文獻中的記憶體元件大部分是使用EEPROM技術，而非嵌入式記憶體元件。雖然有文獻有提出相容於標準製程(嵌入式)之實現方式，但準確度卻會受到非線性寫入機制和元件製程誤差的限制，為了提高解析度，有些文獻使用晶片外部之寫入系統或者外接高解析度比較器，但如此便會提高系統之複雜性。
本研究的主要目標希望在標準0.35微米互補型金氧半製程下設計嵌入式非揮發性類比記憶體，其設計原則著重於非揮發性、操作簡單、快速寫入(寫入時間於<1ms)以及具有高精準度(八位元解析度)等四項特性。本論文中，依據先前我們研究量測的結果，進一步改善寫入速度、破壞性讀取以及精準度等這些特性。經改良後下線量測並與模擬相比較，以及驗證量測結果是否符合原理的推論。除了電路設計上的改變，本論文為了提供類比記憶體電路模擬時的熱載子注入模型，將不同尺寸P-型電晶體萃取出的熱載子效應趨近模型之製程參數(α、β)加以歸納整理，並得出一定規律性之後，便藉此規律性預估不同元件尺寸之熱載子效應趨近模型。最後設計出在標準0.35微米互補型金氧半製程下，非破壞性讀取且有八位元解析度的類比記憶體單元後，提出陣列式類比記憶體電路架構。

第一章 緒論......................... ..................1
1.1 研就動機與目的................................. 1
1.2 研究貢獻....................................... 2
1.3 章節架構...........................................3
第二章 相關文獻回顧................. ..................4
2.1 不同非揮發性記憶體元件架構... ..................4
2.1.1 Diffusion Self-Align元件架構介紹........ 4
2.1.2 Novel MONOS元件架構介紹................. 5
2.1.3 HIMOS元件架構介紹....................... 6
2.1.4 SMCI元件架構介紹........................ 8
2.1.5 Step Split Gate元件架構介紹............. 9
2.2 不同類記憶體自我收斂寫入之電路架構............. 11
2.2.1自我收斂電流型類比記憶體電路............. 11
2.2.2線性調適負回授比較器自我收斂電壓型類比記憶體電
路...........................................12
2.2.3比較器負回授自我收斂電壓型類比記憶體電路. 15
2.2.4脈衝寬度調變(PWM)自我收斂電壓型類比記憶體電
路...........................................17
2.3非揮發性類比記憶體陣列.......................... 19
第三章 模擬閘極電流模型............................... 22
3.1非揮發性記憶體寫入抹除機制模型公式.............. 22
3.1.1傅勒-諾德翰穿隧(Fowler-Nordheim tunneling
effect).................................. 22
3.1.2熱載子注入( Hot Carrier Effect).......... 24
3.2 測試元件...................................... .27
3.3 元件量測數據與趨近模型......................... 29
3.3.1 製程參數萃取............................ 29
3.3.2 傅勒-諾德翰穿隧電流驅進模型............. 31
3.3.3 N-型電晶體閘極電流趨近模型.............. 32
3.3.4 P-型電晶體閘極電流趨近模型.............. 34
3.4 結論........................................... 41
第四章 非揮發性類比記憶體電路設計與量測............... 42
4.1 非揮發性記憶體電路設計......................... 42
4.1.1 電流比較器.............................. 43
4.1.2單增益緩衝放大器......................... 45
4.1.3 整體電路架構............................ 46
4.2 初版晶片量測結果與改良......................... 47
4.3 電路模擬討論................................... 51
4.4 晶片佈局圖與實體晶片........................... 55
4.5 晶片量測結果討論............................... 57
4.5.1量測環境架設............................. 57
4.5.2 實驗量測結果............................ 58
4.6 總結........................................... 67
第五章 電路非理想特性之改善........................... 68
5.1佈局後整體模擬與量測比較討論.................... 68
5.2整體電路問題討論與改善..............................71
5.2.1討論與改善輸出電流IOUT攀升之問
題 .......................................71
5.2.2討論與改善時脈饋入(clock feedthrough)效應之問
題 ..........................................77
5.2.3討論與改善寫入時間的縮短................. 79
5.3完整電路改良後之模擬........................... 79
5.4.總結.......................................... 85
第六章 類比記憶體陣列................................. 86
6.1陣列電路設計................................... 86
6.1.1邏輯閘控制電路 ...........................88
6.1.2電壓準位平移器 ...........................90
6.2 子電路模擬................................... 93
6.2.1邏輯閘控制電路模擬....................... 93
6.2.2電壓準位平移器模擬....................... 94
6.2.3記憶體單元電路模擬....................... 95
6.3.總結......................................... 99
第七章 結論和未來方向................................ 100
7.1結論.......................................... 100
7.2未來方向....................................... 100
參考文獻............................................. 102

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