本篇文章提出新穎的準垂直型(quasi-verticcal)閘極絕緣雙極性電晶體(IGBT)與接面位障蕭基二極體(JBS diode)兩種結構。藉由準垂直結構的設計，此兩種元件能夠與其他元件整合達到積體化，適合應用於積體功率電路(power ICs)。透過半導體元件模擬軟體Medici模擬以及採用HV_0.5μm_5/100V_1P3M製程製作元件。經模擬與量測結果指出，結構中有P-Sinker設計的V-IGBT元件，其正向導通能力比相同條件下的L-IGBT與VDMOS好，因此擁有可積體化和低導通電壓降的優點。而接面位障二極體在常溫和溫度變化下的正向導通能力比相同製程和條件下的PN二極體好，導通和截止所需的關閉時間約為200 ns，只有PN二極體的一半，有低導通壓降和關閉快速的優點。

This thesis studies two novel structures that have low forward voltages—quasi-vertical IGBT and JBS diode. In addition, by incorporating the quasi-vertical design, the proposed devices are able to be integrated with other devices, very suitable in the application of power ICs. The devices were first designed using the simulator MEDICI and then taped-out using HV_0.5μm_5/100V_1P3M process. The simulation and measurement results indicate that the V-IGBTs with P-Sinker design have better forward capability than that of L-IGBT and VDMOS. At room temperature as well as at elevated temperatures, the proposed JBS diodes have lower forward voltage than that of the PN diodes in the same fabrication process. In terms of the turn-off time, it takes 200 ns for the fast JBS diodes to turn off, only half of the time required by the PN diodes.

摘要...........................................................................................................I
Abstract....................................................................................................II
致謝..........................................................................................................III
目錄.........................................................................................................VII
圖目錄.......................................................................................................X
表目錄................................................................................................XVIII

第一章 序論...........................................................................................1
1.1 前言.....................................................................................1
1.2 研究動機與文獻回顧.........................................................1
1.3 論文大綱.............................................................................5
第二章 元件基本原理.........................................................................9
2.1 PN二極體元件基本操作原理............................................9
2.1.1 多數載子與少數載子元件運作機制…..................9
2.1.2 二極體的暫態反應................................................12
2.2 接面位障蕭基二極體(Junction Barrier controlled Schottky
，JBS)結構原理................................................................13
2.3 垂直型閘極絕緣雙極性電晶體(Vertical Insulated Gate
Bipolar Transistors, VIGBT )結構原理...........................14
2.4 崩潰機制介紹…..............…….........................................15
2.4.1 乘積係數(Multiplication coefficient) .................16
2.5 場板(Field plate)結構原理...............................................18
第三章 元件設計及特性模擬.........................................................25
3.1 元件崩潰探討...................................................................26
3.1.1 垂直型PN二極體..................................................26
3.1.2 接面位障蕭基二極體…........................................27
3.1.3 垂直型雙擴散金氧半場效電晶體........................28
3.1.4 閘極絕緣雙極性電晶體…....................................29
3.1.5 接面隔離(Junction isolation)結構.........................29
3.2 正向導通特性模擬與比較...............................................31
3.2.1 垂直型PN二極體.................................................31
3.2.2 接面位障蕭基二極體…........................................31
3.2.3 垂直型雙擴散金氧半場效電晶體........................32
3.2.4 閘極絕緣雙極性電晶體…....................................33
3.3 切換特性模擬與探討.......................................................34
3.3.1 反向回覆(Reverse recovery)表現..........................35
3.3.2尾電流(Tail current) ...............................................35


第四章 元件製作與量測結果分析................................................57
4.1光罩設計與佈局……........................................................57
4.2 垂直型PN二極體與接面位障蕭基二極體...................58
4.2.1 崩潰特性................................................................59
4.2.2 正向導通特性........................................................60
4.2.3 動態切換特性........................................................61
4.3 金屬氧化物半導體場效電晶體(MOSFETs)與閘極絕
緣雙極性電晶體(IGBT)..................................................62
4.3.1 崩潰特性................................................................62
4.3.2 電流電壓特性........................................................64
4.3.3 動態切換特性........................................................67
4.4 閘極絕緣雙極性電晶體(IGBT)基板電流探討...............68

第五章 結論與未來展望..................................................................92
5.1 結論...................................................................................92
5.2 未來展望...........................................................................93
參考文獻................................................................................................94



圖目錄

圖1.1 VDMOSFET結構圖...............................................................6
圖1.2 LDMOSFET結構圖...............................................................6
圖1.3 高壓功率元件的應用.............................................................7
圖1.4 Short-Anode LIGBT結構圖...................................................7
圖1.5 NPN Controlled LIGBT結構圖..............................................8
圖1.6 Quasi-Vertical DMOSFETs結構圖.........................................8
圖1.7 Quasi-Vertical IGBT結構圖....................................................8
圖2.1 PN接面在順向偏壓的少數載子濃度分佈...........................20
圖2.2 金屬-半導體接面在(a)逆向偏壓與(b)順向偏壓在理想狀態
下的能帶................................................................................20
圖2.3 觀察二極體暫態反應的簡單電路........................................21
圖2.4 二極體在切換過程中，隨時間變化的少數載子濃度.........21
圖2.5 二極體在切換過程中，電流對時間的特性.........................21
圖2.6 JBS基本結構圖......................................................................22
圖2.7 單一JBS通道放大圖.............................................................22
圖2.8 （a）JBS在順向偏壓下的工作情形（b）JBS在逆向偏壓
下的工作情形........................................................................22
圖 2.9 VIGBT結構圖......................................................................23
圖2.10 VIGBT等效電路圖...............................................................23
圖2.11 逆向偏壓時PN接面中的基納崩潰機制..............................23
圖2.12 在累增崩潰下，通過空乏區的電子電洞電流分量..............24
圖2.13 (a) 場板在不同偏壓下對空乏區的影響(b) PN接面電極與
場板相連接的效果................................................................24
圖3.1 垂直型PN Diode結構剖面示意圖......................................37
圖3.2 (a)無場板的PN Diode崩潰時的等電位線和空乏區圖
(b)場板長度為5μm的PN Diode崩潰時的等電位線和空乏
區圖........................................................................................38
圖3.3 場板長度對於崩潰電壓的影響.............................................38
圖3.4 為探討JBS元件中P型摻雜間距m對元件崩潰電壓影響的
結構........................................................................................39
圖3.5 P型摻雜間距m對於崩潰電壓的影響.................................40
圖3.6 加入場板和P-Body等設計的垂直型JBS結構...................40
圖3.7 (a)沒有P-Body製程的JBS元件在70V崩潰時的等電位線
和空乏區圖 (b)加入P-Body製程後的JBS元件在121V崩
潰時的等電位線和空乏區圖................................................41
圖3.8 VDMOSFETs結構示意圖....................................................42
圖3.9 VDMOS崩潰時的等電位線和空乏圖..................................43
圖3.10 新穎IGBT結構示意圖.........................................................43
圖3.11 IGBT崩潰時的等電位線和空乏區圖...................................44
圖3.12 由最外圍的P-Sinker所組成的接面隔離(junction isolation)
結構圍繞著主要元件示意圖................................................45
圖3.13 接面隔離結構的安全距離d對於崩潰電壓的影響.............45
圖3.14 探討N型掩埋層到P-Sinker之間距離w對於崩潰影響的模
擬結構示意圖........................................................................46
圖3.15 N型掩埋層到P-Sinker之間距離w對於崩潰影響的模擬結
果............................................................................................46
圖3.16 (a) w等於2μm崩潰電壓為114V時的空乏區和電流線分佈
圖(b) w等於3μm崩潰電壓為124V時的空乏區和電流線分
佈圖........................................................................................47
圖3.17 垂直型PN二極體在不同溫度下的I-V特性模擬曲線.......47
圖3.18 JBS二極體在不同溫度下的I-V特性模擬曲線..................48
圖3.19 垂直型PN二極體、JBS二極體與結合PN-Sinker的JBS二
極體操作在電流密度為100A/cm2和不同溫度下的特性模
擬曲線....................................................................................48
圖3.20 VDMOSFETs使用Linear extrapolation法所估計的臨界導通
電壓值約為5V.......................................................................49
圖3.21 室溫300K且在不同閘極電壓下模擬所得到的電流密度對
汲極電壓I-V曲線圖..............................................................49
圖3.22 模擬在電流密度對汲極電壓I-V曲線圖中在A點和B點情
況下的電流線和空乏區示意圖............................................50
圖3.23 相同操作條件下IGBT元件有無P-Sinker結構和VDMOS
元件的正向導通電壓(@100 A/cm2)比較.............................50
圖3.24 模擬元件底下2μm、閘極電壓為10V和陽極偏壓為1.5V
下少數載子(電洞)分佈圖.....................................................51
圖 3.25 室溫300K並在不同閘極電壓下模擬IGBT元件的電流密度
對汲極電壓I-V曲線..............................................................51
圖3.26 室溫300K閘極電壓為15V下比較IGBT和VDMOS兩元
件的電流密度大小................................................................52
圖 3.27 在JBS元件P-Sinker端加入P+重摻雜以提升切換特性的結
構示意圖................................................................................52
圖3.28 模擬二極體切換特性時所採用的電阻負載(Resistive load)
電路架構................................................................................53
圖3.29 固定相同操作電流以及反向偏壓下模擬PN二極體、JBS
和JBS的Sinker端加入P+摻雜三種不同元件的切換特
性............................................................................................53
圖3.30 PN二極體、JBS和JBS的Sinker端加入P+摻雜三元件的
正向導通電壓(@100A/cm2)對關閉時間(Turn-off time)的比
較............................................................................................54
圖3.31 改良型(Modified) VIGBT結構3D剖面圖.........................54
圖3.32 模擬IGBT切換特性時所採用的電阻負載(Resistive load)電
路架構....................................................................................55
圖3.33 固定相同操作電流下模擬VIGBT、改良型VGBT(M-VIGBT)
和VDMOS三種元件的切換特性...........................................55
圖3.34 VIGBT、M-VIGBT和VDMOS三元件固定閘極電壓10V
下的正向導通電壓(@100A/cm2)對關閉時間比較................56
圖4.1 功率元件光罩設計圖(面積為4mm*2mm) ............................70
圖4.2 VDMOS元件中NBL層分別採(a)傳統方形設計和(b)改良型
設計光罩示意圖......................................................................70
圖4.3 (a)為垂直型PN二極體的layout圖(面積約為340μm*365μm)
(b)為實際元件拍攝圖.............................................................71
圖4.4 (a)為JBS二極體的layout圖(面積約為340μm *365μm)
(b)為實際元件拍攝圖.............................................................71
圖4.5 (a)為JBS二極體的layout圖(面積約為320μm *96μm)
(b)為實際元件拍攝圖.............................................................72
圖4.6 使用371A所量得的曲線，並定義電流急劇竄升時的點為崩
潰電壓......................................................................................73
圖4.7 使用HP4145B量測三種不同P型緩衝層濃度設計的PN二
極體，正向偏壓時的電流對電壓曲線....................................73
圖4.8 溫度變化下PN與JBS元件電流密度對電壓曲線比較.........74
圖4.9 Inductive load switching電路架構示意...................................75
圖4.10 實際的inductive load switching測試電路............................76
圖4.11 將待測元件固定在相同的電流操作密度(J=2860A/cm2)，並透
過示波器觸發(trigger) gate drive所輸入的第二個方波前
緣..............................................................................................76
圖4.12 PN二極體在導通和截止時的瞬間波形................................77
圖4.13 JBS二極體在導通和截止時的瞬間波形...............................77
圖4.14 (a)為P-Sinker到NBL間距不相同的V-IGBT光罩圖(b)為實
際元件拍攝圖(面積約為337μm *210μm).............................79
圖4.15 P-Sinker垂直擴散至NBL之中結構示意圖..........................80
圖4.16 模擬P-Sinker到 NBL間距為1.8μm的結構在41V崩潰時的
等電位線和空乏區圖..............................................................80
圖4.17 模擬P-Sinker到 NBL間距為1.8μm的結構在41V崩潰時的
3D電場圖.................................................................................81
圖4.18 模擬P-Sinker到 NBL的不同間距對崩潰電壓的影響…...81圖4.19 利用saturation extrapolation法並設定IGBT元件閘極與陽極
電壓相等(VG =VAnode = 10V)，以確保操作在飽和區下所估得
的臨界導通電壓約4.8V..........................................................82
圖4.20 (a)為L-IGBT的layout圖(面積約為315μm *210μm)(b)為實際元件拍攝圖..........................................................................83
圖4.21 採用單一多晶矽閘極搭配一個Sinker設計的元件其電流密度對電壓比較..........................................................................83
圖4.22 為V-IGBT與L-IGBT採單個和多個多晶矽閘極設計下，電
流密度對電壓相互重疊比較圖..............................................84
圖4.23 在相同閘極電壓15V下的電流密度對電壓量測結果...........84
圖4.24 V-IGBT在不同溫下的電流密度對電壓曲線.........................85
圖4.25 為V-IGBT採單一多晶矽閘極與一個Sinker設計下，其臨界
導通電壓對溫度變化作圖......................................................85
圖4.26 (a)為VDMOS在大尺寸設計下的layout圖(b)為實際元件拍
攝圖(面積約為1420μm *437μm) ..........................................85
圖4.27 大尺寸的VDMOS在不同閘極電壓下的電流對電壓圖…...86
圖4.28 大尺寸的V-IGBT在不同閘極電壓下的電流對電壓圖…...86
圖4.29 將V-IGBT和VDMOS兩元件在不同閘極電壓下的電流密度
對電壓圖重疊..........................................................................87
圖4.30 Inductive load switching電路架構示意.................................87
圖4.31 將待測元件固定在相同的電流操作密度(J=150A/cm2)，並透
過示波器觸發gate drive輸入的第二個方波下緣.................88
圖4.32 V-IGBT元件的尾電流量測結果.............................................89
圖4.33 VDMOS元件的尾電流量測結果............................................89
圖4.34 外環由四個P-ISO所圍繞著的V-IGBT元件(每個間隔為
20μm) .......................................................................................90
圖4.35 透過模擬在相同條件操作下的VIGBT元件，其電流線分佈圖..............................................................................................91
圖4.36 模擬一個P-Sinker搭配兩個通道設計的VIGBT元件，其電
流線分佈圖..............................................................................91
圖5.1 改變製程流程下所提出的結構...............................................93








表目錄

表3.1 模擬圖3.1結構所使用到的元件參數.................................37
表3.2 模擬圖3.4結構所使用到的元件參數.................................39
表3.3 模擬圖3.6結構所使用到的元件參數..................................41
表3.4 模擬圖3.8結構所使用到的元件參數..................................42
表3.5 模擬圖3.10結構所使用到的元件參數...............................44
表4.1 NBL層分別採傳統方形和改良型設計下其量測結果…..70
表4.2 實際元件下線規格和名稱....................................................70
表4.3 模擬以及使用儀器SONY 371A curve tracer和HP 4145B所
量得的結果............................................................................72
表4.4 P型摻雜間距不相同的JBS元件對於崩潰電壓的模擬以及
量測結果................................................................................74
表4.5 Inductive load switching電路實驗材料表...........................75
表4.6 實際下線元件規格和名稱.....................................................78
表4.7 實際下線元件規格和名稱.....................................................78
表4.8 為使用型式A方法所量得的正向崩潰電壓........................79
表4.9 為使用型式B方法所量得的正向崩潰電壓........................79
表4.10 實際下線元件規格和名稱.....................................................82
表4.11 Inductive load switching電路實驗材料表............................88
表4.12 在閘極電壓25V、陰極接地和陽極電壓2V導通下，使用
A~D四種量測條件所量得的基板對陽極電流比例............90

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