頻率合成器電路在無線的通訊系中扮演了一個非常重要的角色。不論是在接收機或是發射機中都需要頻率合成器電路來產生本地的震盪頻率。而急速成長的無線區域網路市場也極力的帶動高傳輸速率與傳輸量的需求。因此，在如此困難的挑戰之下設計一個高速且低雜訊的頻率合成器電路變成是一個非常重要的趨勢。

在本論文中，我們設計即呈現了一個操作在5GHz以整數型架構的頻率合成器，並將其功率消耗做最佳化的設計。此外增加了一個類比式的迴授改善電荷幫浦中電流源不匹配的問題。振盪器電路使用的是傳統的LC震盪電路採用並聯開關的方式，降低壓控振盪器的增益以達到整體迴路低雜訊的效果。在本設計之中，振盪器的相位雜訊在1MHz的Offset頻率達到了-112dBc/Hz的效能，換算成FOM指數約為185。在除頻器的設計中，我們採用電流式邏輯為基底的電路，他可以使得除頻器電路達到寬頻的除頻效果。根據Post-Layout 的模擬結果，前四級除頻器的輸入頻率讓其可正確可除範圍約為1.2 ~ 7.3 GHz。如此寬頻的設計使得它可以避免製程與溫度的變異。

最後，本研究採用的是TSMC 0.18mm 1P6M RF製程來實現頻率和成電路晶片，整體的電路的面積約為1.2 x 1.3mm2。

A Frequency Synthesizer plays an important role in wireless communication systems. Both transmitter and receiver need the synthesizer to generate local oscillation frequency. The growing wireless LNA market has generated increasing interest in technologies that enable higher data rates and capacity compared to those of previous implementation. Hence, design a low power frequency synthesizer with good noise performance is a significant work.
In this work, a phase locked loops based integer-N frequency synthesizer with optimal power consumption is presented. This PLL employs an analog feedback charge pump circuit for low noise application. The oscillator is implemented by conventional LC-tank, with switch capacitance to achieve low spur and low phase noise. At 5.12GHz, the VCO system demonstrates a phase noise of -113dBc/Hz at 1MHz offset with dissipation 1.5mA at a 1.2-V supply. This corresponds to a FOM of 188dBc/Hz/mW. For the divider chain of this work, current-mode logic based frequency dividers are adopted in four-stage cascaded-dividers after LC based buffer. This will allow the system to generate a wide-locking-range characteristic. According to the post-layout simulation of the CML divider chain, they achieve a 1.2 to 7.3GHz locking range wide. This result shows that the divider chain implemented can correctly operate under possible PVT variations.
Finally, this frequency synthesizer has been fabricated in a TSMC 0.18 um 1P6M RF/Mixed-Mode Process. The whole circuits occupy an area of 1.2 x 1.3mm2.

致謝 i
摘要 ii
Abstract iii
索引 iv
附圖索引 vii
附表索引 ix
第一章 緒論 1
1-1. 研究動機 1
1-2. 論文組織 2
第二章 頻率合成器之基本理論 4
2-1. 鎖相迴路基本原理(PLLs Basic) 4
2-2. 鎖相迴路線性化模型(Linear Model of PLLs) 5
2.2.1 壓控振盪器(Voltage Controlled Oscillators, VCOs) 6
2.2.2除頻器(Frequency Divider, FD) 7
2.2.4低通濾波器(Low Pass Filter, LPF) 10
2.2.4.1 Second-order, Type-2 PLL 11
2.2.4.2 Third-order, Type-2 PLL 13
2-3. 鎖定時間(Locking Time) 15
2-4. 相位雜訊(Phase Noise) 16

第三章 頻率合成器之電路設計 19
3-1. 系統架構(Systems Architecture) 19
3-2. 行為模擬(Behavior Model) 20
3-3. 電路架構模擬與設計(Circuit Implementation) 22
3.3.1 相位頻率檢測器(Phase and Frequency Detector, PFD) 22
3.3.2 電荷幫浦電路(Charge Pump Circuits, CP Circuits) 23
3.3.3 壓控振盪器電路(Voltage Controlled Oscillators, VCOs) 28
3.3.4緩衝器(Buffers) 32
3.3.5除頻器電路(Divider Circuits) 33
3.3.5.1電流式除頻器電路(CML Based Frequency Divider Circuits) 33
3.3.5.2電流式可程式化除頻器電路(CML Based Programmable Frequency) 38
3-4. 整體迴路模擬結果(Simulation of PLL Closed Loop) 42
第四章 量測環境與佈局考量 44
4-1.佈局考量(Layout Consideration) 44
4-2.PCB 板設計(Design of PCB) 45
4.2.1 PCB板設計(Design of PCB) 46
4.2.2 量測環境(Measurement Environments) 48
4.2.3 FPGA控制訊號(FPGA Control Signals) 50
4-3.量測結果(Measurement Results) 51
第五章 結論與後續建議事項 54
5.1.後續建議事項(Suggestion) 54
5.2.結論(Conclusions) 55
參考文獻 56

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