本論文提出一種新型影像感測讀出電路，並摒棄傳統光電流充取電容方式，希望以即時的電流電壓轉換器，在低照度下亦能達到即時輸出的影像感測。在電流電壓轉換器後接上相關性雙取樣電路(CDS，Correlated Double Sampling)，利用周邊數位控制電路，分別將重置訊號與曝光訊號儲存在電容裡，並在輸出時將兩訊號相減，可有效降低因製程變異所造成的固定圖樣雜訊(FPN, Fixed-Pattern Noise)。
晶片實作部分是透過國家晶片中心，在TSMC 0.35 um SiGe BiCMOS 標準製程下，分別實現3×3以及63×63像素陣列，整個系統包括：
①SiGe製程下，BJT 的基集接面(BC junction)感光二極體，為
本實驗室所開發的優異光電元件，其光電流可從pA到40uA的數
量級。
②新型電流電壓轉換電路，將大範圍的輸入光電流，轉變為小範圍
的電壓輸出擺幅，提供後端電路使用。
③相關雙取樣電路，使用取樣電容儲存重置訊號與曝光訊號，將兩
端相減取得光感測器轉換成之光電壓訊號。
④常數轉導偏壓(Constant Gm Bias)電路提供一個與電源供應電壓
無關之偏壓供其他電路使用。
⑤周邊數位控制電路，將整體晶片控制序列，與類比電路部分整
合，達成系統晶片化(System On a Chip)。

量測部分以一穩定光源照射感光區域，並使用FPGA或晶片內部本
身電路產生所需之控制時脈，完成整體電路之操作；最後以數位
示波器量測輸出端得到光電壓訊號。

We present a novel image sensor that uses the new read out circuit. This work is different from other CMOS imagers which have to sense the voltage drop after the integration time because of low photocurrent charging parasitic capacitance. New read out circuit converts wide range photo current into narrow range voltage, and contributes it to the usage of backend circuit. The photodiode fabricated in 0.35 um SiGe BiCMOS technology has linear wide-dynamic-range photocurrent (~ pA to ~ 40 uA) under wide-dynamic-range illumination (0.0lux. to 460000 lux.). So we can sense the photocurrent directly without accumulating charges. The novel image sensor is constructed by:
(1) Photodiode, whose detecting region is base-collector
(BC) junction, converts the light intensity into the
photocurrent.
(2) New read out circuit that obtains the wide dynamic
range photocurrent from the pixel and outputs the
voltage signal.
(3) Correlated Double Sampling (CDS) circuit that cancels
the fixed-pattern noise (FPN) which results from
process variations.
(4) Constant gm bias circuit contributes supply-
independent-biasing to the imager.
(5) Peripheral digital control circuit is integrated with
analog circuit and pixel array, which achieves the
system-on-a chip design.
This work has been fabricated in TSMC 0.35 um SiGe BiCMOS technology. Experimental results confirm the ability of the wide-dynamic range readout circuit.

第一章 前言 ............................................1
1.1 研究動機 ...........................................1
1.2 本論文研究重點......................................2
1.3 本論文章節安排 .....................................2

第二章 半導體光感測元件與CMOS影像感測器之架構與特性 ....4
2.1 半導體光感測元件 ...................................4
2.1.1基本知識 ..........................................4
2.1.2 半導體材料感光原理 ...............................5
2.1.3 各種半導體光感測器 ...............................7
2.2 CMOS影像感測器的基本原理與性質 ....................11
2.2.1 影像感測流程 ....................................12
2.2.2 影像感測器的基本性質 ............................13
2.2.3 CMOS影像感測器的基本像素架構 ....................15

第三章 相關研究發展現況 ...............................19
3.1 高動態範圍影像感測原理 ............................19
3.2 高動態範圍影像感測架構 ............................20
3.2.1 電流式像素架構 ..................................20
3.2.2 對數式像素架構 ..................................21
3.2.3 數位式像素架構 ..................................23
3.2.4 總結 ............................................24

第四章 高動態範圍影像感測器之設計 .....................25
4.1 像素設計 ..........................................26
4.2 光電流轉電壓讀取電路設計 ..........................27
4.2.1 設計概念.........................................27
4.2.2 讀取電路操作方式.................................30
4.3 相關二次取樣電路設計 ..............................31
4.3.1 設計概念.........................................32
4.3.2 相關二次取樣電路操作方式.........................34
4.3.3 行電路佈局.......................................34
4.4 偏壓電路設計 ......................................35
4.5 時脈控制電路設計 ..................................37
4.5.1 晶片規格設計.....................................37
4.5.2 行、列控制電路設計...............................38
4.5.3 其他控制電路部分設計.............................39
4.6 整體電路時脈控制 ..................................41

第五章 模擬結果 .......................................43
5.1 像素電路等效模型 ..................................43
5.2 偏壓電路模擬結果 ..................................44
5.3 3 × 3像素陣列模擬結果 .............................46
5.3.1 模擬結果 ........................................46
5.3.2 晶片佈局結果 ....................................49
5.4 63 × 63像素陣列模擬結果 ...........................51
5.4.1 數位電路部分模擬結果 ............................51
5.4.2 整體電路模擬結果 ................................54
5.4.3 晶片佈局結果 ....................................58

第六章 晶片量測與分析 .................................60
6.1 量測環境建立 ......................................60
6.1.1 量測儀器 ........................................60
6.1.2 FPGA控制信號 ....................................62
6.2 3×3影像感測器量測結果 .............................63
6.2.1 暫態量測 ........................................63
6.2.2 量測結果 ........................................64
6.2.3 量測結果討論 ....................................70
6.3 63×63影像感測器量測結果 ...........................71
6.3.1 數位控制訊號量測 ................................71
6.3.2 偏壓電路量測 ....................................72

第七章 總結 ...........................................73
7.1 成果整理 ..........................................73
7.2 後續研究改進之建議 ................................73

參考文獻 ..............................................74

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