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作者(中文):黃鯖珮
作者(外文):Huang, Cing-Pei
論文名稱(中文):CMOS MEMS微加速度計與低雜訊電容感測電路之整合及實現
論文名稱(外文):Integration and Implementation of CMOS-MEMS Microaccelerometer and low-noise Capacitive Sensing Circuits
指導教授(中文):陳榮順
指導教授(外文):Chen, Rongshun
學位類別:碩士
校院名稱:國立清華大學
系所名稱:動力機械工程學系
學號:9733615
出版年(民國):99
畢業學年度:98
語文別:中文
論文頁數:63
中文關鍵詞:CMOS MEMS微加速度計電容感測電路
外文關鍵詞:CMOS MEMSAccelerometerCapacitive Sensing Circuit
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本研究利用tsmc 0.35μm 2P4M標準CMOS製程平台以及相容於CMOS後製程,設計及製作平面式加速度計並整合其電容感測電路。本研究先實現單軸加速度感測器進而推廣至雙軸感測器。雙軸感測共用一質量塊並預期能同時量測平面X、Y方向加速度;而元件感測介面是採用全差動式,有更高的敏感度及較佳抵抗雜訊的能力。由於感測訊號極小,因此考量雜訊干擾並建立雜訊模型和設計符合元件之電容感測介面電路。電路端設計目標為低雜訊且具有可調靈敏度之功能,並探討元件與電路整合時所需考量的議題。本研究成功地將單軸加速度計與感測電路整合,量測結果其靈敏度為6.1 mV/g。
This study presents a capacitance sensing circuit with low noise and tuned-sensitivity by integrating an in-plane microaccelerometer, included one-axis and dual-axis sensors. The dual-axis microaccelerometer is monolithic using single proof-mass to sense in-plane directions. The interface of microaccelerometer is fully-differential which is capable of reducing common-mode noise and offering higher resolution. Futhermore, this work constructs a noise model to study how to suppress the noise which influences the sensitive signal effectively. The microstructure and the capacitive sensing circuit were fabricated through tsmc 0.35 μm mixed-signal 2P4M polycide 3.3/5 V process. As a result, the microstructure with one-axis sensing is successfully integrating with capacitive sensing circuit. Experimental results showed that the whole chip sensitivity measurement is 6.1 mV/g.
摘要 I
Abstract II
致謝 III
目錄 IV
圖目錄 VI
表目錄 X
第一章 緒論 1
1.1 前言 1
1.2 研究背景與動機 1
1.3文獻回顧 3
1.3.1 微加速度計 3
1.3.2 電容感測電路 6
1.4 本文大綱 10
第二章 系統架構與分析 11
2.1整體系統架構 12
2.2微加速度計等效結構模型分析 14
2.2.1彈簧設計 15
2.2.2加速度計應力補償外框 16
2.2.3加速度計感測介面 17
2.3元件與電路整合之設計考量 19
2.4電容式感測電路設計 23
第三章 模擬結果與討論 31
3.1微加速度計設計與模擬 31
3.2前置放大器模擬 37
3.3 光罩佈局 44
第四章 後製程流程與實驗結果 48
4.1元件後製程流程 48
4.2元件端量測結果 49
4.3 加速度感測器量測結果 53
4.3.1 晶片封裝與架設 53
4.3.2 晶片量測結果 55
第五章 結論與未來工作 59
5.1 結論 59
5.2 未來工作 60
參考文獻 61
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