唯讀記憶體是一種非揮發性記憶體，時常在內嵌式系統中，用來儲存大量固定資訊和系統程式。唯讀記憶體包含反或閘型和反及閘型兩種，反及閘型唯讀記憶體由於有較高密度但速度較慢，適合低速度的應用。當製成技術不停的演進，低電壓和高速度成為相當重要的設計目標，在低電壓下，反及閘型唯讀記憶體擁有比反或閘型唯讀記憶體更高的穩定性，因此設計一種在低電壓下仍有高操作速度的反及閘型唯讀記憶體有其必要性。

　　在反及閘型唯讀記憶體的設計中，碼相關的讀取電流、位元線與反及閘串間的電荷分享、相鄰位元線間的串音效應和位元線漏電流限制了反及閘型唯讀記憶體的操作頻率和最低操作電壓。在過去的研究中，對於這些問題己經提出一些解決辦法。但有些方法會犧牲部份操作速度。

　　在此篇論文中，我們提出碼反轉的方式，在不增加位元線漏電流的情況下，解決反及閘型唯讀記憶體讀取電流較小的問題。借由提高讀取電流和漏電流的比例，使電路能操作在更高的速度和更低的電壓。為了實現低電壓設計和提高電壓操作區域，我們使用動態源極線架構[1]降低電荷分享、串音效應和位址線漏電流的問題，並使用位址線追蹤架構[2]作為信號時間控制。

　　我們使用90奈米互補式金氧半導體製程技術，製作兩顆256kb反及閘型唯讀記憶體晶片，一顆使用一般反及閘型唯讀記憶體電路的儲存架構，一顆使用提出的碼反轉的儲存方式。使用碼反轉的反及閘型唯讀記憶體晶片可以操作在1V到0.26V電壓區間，比不使用碼反轉的電路在低電壓下提高約25%的操作頻率，在0.3V操作電壓下仍有9MHz的操作速度。

Read-only memory(ROM) is a non-volatile memory which is commonly used in embedded system for large fix information storage and system program storage. ROM include NOR-type and NAND-type. NAND-type ROM is used for lower speed application due to high density but lower operation frequency. When process technology scaling to nanometer, low voltage and high speed deisgn become a main goal. Since NAND-type ROM has higher reliability in low voltage compare with NOR-type ROM, a low voltage and high speed NAND-type ROM is necessary.

Code-dependent cell current, charge sharing between bitline(BL) and NAND string, crosstalk and BL leakage in NAND-type ROM limit the operation frequency and minimum operation voltage(VDDmin). Previous studies have proposed some methods to solve these issues.

We proposed a code-inversion scheme to solve the problem of small read current in
NAND-type ROM. Operation frequency and minimum operation voltage is improved due to increase the on-off current ratio. To achieve low voltage design and high operation range, dynamic split sourceline scheme [1] is used in our design to reduce charge sharing, crosstalk and bitline leakage. BL tracking scheme [2] is used in our design for timing control.

A 256kb NAND-type ROM macros is implement in 90nmCMOS technology, which can operate from 1V to 0.26V, improving 25% operation frequency. The measurement result shows the propose scheme has 9MHz operation speed at 0.3V.

1 Introduction 1
2 Issues of NAND-type ROM 3
2.1 Comparison for NAND-type and NOR-type . . . . . . . . . . . . . . . 3
2.2 Conventional NAND-type ROM . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 Structure and Operation . . . . . . . . . . . . . . . . . . . . . 7
2.2.2 Code-dependent Cell Current . . . . . . . . . . . . . . . . . . 9
2.2.3 Charge Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.4 Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.5 Bitline Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 On-off Current Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Proposed Scheme 24
3.1 Code-inversion Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.1 Single-bit Code-inversion . . . . . . . . . . . . . . . . . . . . 24
3.1.2 Multi-bits Code-inversion . . . . . . . . . . . . . . . . . . . . 25
3.1.3 Dual-path Data-out . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2 On-to-Off Current Ratio Improvement . . . . . . . . . . . . . . . . . . 28
3.2.1 Code-inversion with Keeper . . . . . . . . . . . . . . . . . . . 28
3.2.2 Code-inversion with Sourceline Control . . . . . . . . . . . . . 30
3.2.3 Code-inversion with Dynamic Reference Voltage . . . . . . . . 32
3.3 Area Penalty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3.1 NAND-type ROM area reduction . . . . . . . . . . . . . . . . 35
3.3.2 Flag-table area penalty . . . . . . . . . . . . . . . . . . . . . . 36
4 Macro Implementation 39
4.1 Macro Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.1 Conventional NAND-type ROM Architecture . . . . . . . . . . 39
4.1.2 Proposed NAND-type ROM Architecture . . . . . . . . . . . . 40
4.1.3 Flag-Table Structure . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.4 Dual-path Sensing Output Scheme . . . . . . . . . . . . . . . . 43
4.1.5 Replica Bitline . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1.6 Dynamic Virtual Guardian . . . . . . . . . . . . . . . . . . . . 45
4.1.7 Dynamic Split Sourceline . . . . . . . . . . . . . . . . . . . . 46
4.1.8 Dynamic Reference Voltage . . . . . . . . . . . . . . . . . . . 48
4.2 Macro Layout for Proposed NAND-type ROM . . . . . . . . . . . . . 49
4.3 Testchip Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5 Comparison and Experimental Results 51
5.1 Comparison with Conventional Design . . . . . . . . . . . . . . . . . . 51
5.2 Speed Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2.1 Power Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.1 Test-chip Photo . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.2 Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6 Conclusion 62
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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