在本篇論文中，主要是呈現一個超低複雜度手機與高效能閉迴路多輸入多輸出通訊的完整設計與實現，其內容包含先前相關研究的研讀，系統模擬與架構設計，以及系統晶片平台驗證與實現。

在傳統通訊系統，多輸入多輸出(multi-input multi-output, MIMO)技術已被廣泛使用於增加資料傳輸率以及提高系統效能，假使通道狀態資訊(channel state information, CSI)能夠進一步在發射端獲得，如此就可達到比傳統上有更好的效能。許多有關於閉迴路多輸入多輸出(colsed-loop MIMO)研究包括幾何平均分解法(geometric mean decomposition, GMD)的相關聯合收發機已經被討論過。根據這些經過充分研究的方法，本論文提出了一個發射天線選擇機制(Transmitter antenna selection, T-AS)應用於幾何平均分解法結合湯林森-何洛緒瑪預編碼 (Tomlinson-Harashima precoding, THP)的聯合收發機。在分時雙工(time-division duplex, TDD)系統，此架構加強一般幾何平均分解法結合湯林森-何洛緒瑪預編碼的效能並且補償了此方法在情況不佳的通道下之缺陷。對於不同發射天線選擇組態，由其訊雜比改善0.1dB所需的複雜度的分析結果，可以得知使用4x6的發射天線選擇是最好的決定。從浮點數模擬結果來看，當誤碼率為10-2，.i. i. d. 通道下，此提出的收發機有著比開放迴路的垂直-貝爾實驗室分層空實編碼好7dB的訊雜比改善。

從硬體複雜度觀點來看，提出許多修改與簡化架構來節省硬體的使用。對於聯合收發機設計來說，通道分解是最複雜的運算。為了省掉在手機端的幾何平均分解法運算，考慮了有效率的解碼矩陣量化與重建。利用一點點的頻寬，只傳送所需的解碼矩陣碼字到手機端，如此就可以簡化手機端的運算。相較於傳統的通道分解運算，此方法可節省手機端一半以上的運算複雜度。在場效可規劃邏輯陣列(FPGA)板上，收發機的最大操作時脈頻率可達到50 MHz，而對應的最大資料吞吐量可到達120 Mbps，此聯合收發機透過模擬和仿真的結果比對證明了功能的正確性。

最後，將聯合收發機置於系統晶片平台作實現，以軟硬體協同驗證的方法對所提出的架構作驗證與除錯。在驗證平台中，採用圖片檔案作為傳輸媒介。藉由系統晶片平台上的LCD螢幕，設計者可以直接在螢幕上看到在不同的通道環境中接收端解出來的結果。在系統晶片平台，收發機的最大操作時脈頻率可達到10 MHz，而對應的最大資料吞吐量可到達120 Mbps。

In this thesis, specification study, system simulation, architecture design and logic design along with SoC platform implementation of a high performance closed-loop MIMO communications with ultra low complexity handset is presented.

In order to provide the better link quality and/or increase the transmission data rate in communications, MIMO techniques are applied in the communication systems. Recently, the channel state information (CSI) may be gathered by the transmitter itself exploiting channel reciprocity in time-division duplex (TDD) systems. It has attracted considerable attention since that can achieves better performance than conventional ones. Several types of closed-loop MIMO systems for wireless communication are discussed and the related MIMO transceiver design based on Geometric Mean Decomposition are also introduced. This thesis proposes an efficient and practicable MIMO transceiver in which transmitter antenna selection is applied to geometric mean decomposition (GMD) which is combined with Tomlinson-Harashima Precoding (THP) in TDD system. This work enhances the conventional GMD-THP and compensates the deficiency of the algorithm under ill-conditioned channel in TDD system. From the floating-point simulation results, the proposed transceiver can achieve about 7 dB SNR improvement over the open-loop VBLAST counterparts at BER=10^(-2) under i.i.d. channel. Moreover, we analyze the computation complexity with various Tx antenna selection (T-AS) configuration for 0.1dB gain improvement. From the analysis result, we can decide that 4 x 6 transmitter antenna selection is the best choose.

Simulations are based on the MIMO fading channel model with white noise. The elements in the channel matrix are assumed i.i.d. complex Gaussian random variable with zero mean and variance of 0.5 per dimension. Simulations are under flat fading and quasi-stationary environment.

In view of hardware complexity, some modified schemes and hardware simplifications are presented to save the VLSI design cost. In order to save the GMD computation at the handset, we also take the decoder quantization/reconstruction into consideration. Make use of a little bandwidth, we just send the needed decoder codewords to the handset. Then, it can be simple for the handset. Because of quantized decoder, we must do some modifications to GMD-THP.
The proposed work can save more than 60% computational complexity at the handset compared with that of the GMD scheme is comparable to the conventional linear transceiver schemes. In the hardware design, most of all the functional block is fully implemented while except for SVD part. Since there are many approaches to the SVD and it is not our main contribution to implement it. The total equivalent gate count of proposed work at the handset is 109,101. The hardware cost of the proposed work compared to another transceiver scheme for 4 x 6 transmitter antenna selection
(T-AS) can save 60%. Furthermore, if we consider the hardware cost of SVD, it can save more than 60%. The maximum operating clock rate of the transceiver can achieve about 50 MHz and the corresponding maximum throughput is 120 Mbps for 64-QAM in FPGA emulation.

Finally, a MIMO joint transceiver is implemented on a SoC platform which is realized to do the hardware/software (HW/SW) co-verification strategy to debug the proposed architecture. In this thesis, which introduces the figure file to be the transmission media. Designer could verify the decoded results in various environment by liquid crystal display (LCD) panel. The maximum operating clock rate of the transceiver can achieve about 10 MHz and the corresponding maximum throughput is 16 Mbps for 16-QAM on SoC platform.

1 Introduction 1
1.1 Overview of Wireless Communication Systems . . . . . . . . . . . . . . . . 1
1.2 Multiple Input Multiple Output Techniques . . . . . . . . . . . . . . . . . . 2
1.2.1 Open-Loop MIMO Communication Systems . . . . . . . . . . . . . 2
1.2.2 Closed-Loop MIMO Communication Systems . . . . . . . . . . . . 3
1.3 Motivation of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 MIMO Communication Systems 7
2.1 Overview of MIMO Techniques . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2 Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3 Spatial Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 MIMO Channel Decomposition . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 Singular Value Decomposition (SVD) . . . . . . . . . . . . . . . . . 15
2.2.2 LU Decomposition (LUD) . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.3 Geometric Mean Decomposition (GMD) . . . . . . . . . . . . . . . 16
2.2.4 Uniform Channel Decomposition (UCD) . . . . . . . . . . . . . . . 18
2.3 MIMO Channel Estimation in TDD and FDD Systems . . . . . . . . . . . . 18
3 MIMO Transceiver Design Based on Geometric Mean Decomposition 21
3.1 GMD-QR in TDD system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 GMD-THP in TDD system . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 GMD-QR with Antenna Selection in FDD system . . . . . . . . . . . . . . . 25
3.3.1 Modified GSO-based Antenna Selection Algorithm . . . . . . . . . . 27
3.3.2 Modified Sequential Vector Quantization . . . . . . . . . . . . . . . 28
3.4 Proposed MIMO Transceiver Design in TDD system . . . . . . . . . . . . . 31
3.5 Complexity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4 System Design 37
4.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2.1 Mathematical Model . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2.2 Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2.3 SNR Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3 Architecture Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3.1 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3.2 Antenna Selection Combined with GMD-THP . . . . . . . . . . . . 43
4.3.3 CSIR Generation and Reconstruction . . . . . . . . . . . . . . . . . 48
4.4 Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.4.1 Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.4.2 System Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.4.3 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . 55
4.5 Word-Length Determination . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.5.1 Word-length Determination Method . . . . . . . . . . . . . . . . . . 57
4.5.2 Word-length in Proposed Architecture . . . . . . . . . . . . . . . . . 59
4.5.3 Fixed-Point Simulation Results . . . . . . . . . . . . . . . . . . . . 62
5 Logic Design 65
5.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.2 Datapath at the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.2.1 Transmitter Antenna Selection . . . . . . . . . . . . . . . . . . . . . 66
5.2.2 Geometric Mean Decomposition . . . . . . . . . . . . . . . . . . . . 70
5.2.3 CSIR Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.2.4 Modified Gram-Schmidt QR . . . . . . . . . . . . . . . . . . . . . 75
5.2.5 Tomlinson-Harashima Precoder . . . . . . . . . . . . . . . . . . . . 78
5.3 Datapath at the Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.1 CSIR Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.2 Modified Gram-Schmidt QR . . . . . . . . . . . . . . . . . . . . . 83
5.3.3 Diagf~ Rg¡1 and Detector . . . . . . . . . . . . . . . . . . . . . . . . 84
5.4 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.5 FPGA Emulation and Measurement . . . . . . . . . . . . . . . . . . . . . . 88
5.5.1 FPGA Board and Features . . . . . . . . . . . . . . . . . . . . . . . 88
5.5.2 FPGA Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.5.3 Hardware Cost Analysis . . . . . . . . . . . . . . . . . . . . . . . . 91
5.5.4 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.5.5 Discussion and Comparison . . . . . . . . . . . . . . . . . . . . . . 91
6 SoC Platform Evaluation 99
6.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.2 SoC Platform Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.2.1 Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.3 Integration and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.1 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.2 HW/SW Co-verification . . . . . . . . . . . . . . . . . . . . . . . . 107
6.4 Emulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.4.1 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7 Discussions and Conclusions 113
7.1 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

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