在本論文中，設計了一個應用於多頻帶的頻譜接收器，並且用電路去實現這個設計，此偵測器擁有了Thomson所提出的適應性多訊窗頻譜估測(AMTSE)，具有非參數估測的特性，應用在寬頻(Wide-Band)的多頻帶(Multiband)頻譜掃描上可以達到盲估測 (Blibd-Sensing) 達成高可靠度的優點 ，並且可以根據環境參數不同去調整各頻帶的權重，達成抗雜訊的好處，此偵測器採用了以Neyman-Pearson的規範，提出了一個以自由度參數(Degree of Freedom)為基準的臨界值判斷法，在一次寬頻的掃描中可以獲得所有子頻帶的資訊跟相對應的臨界值，對於偵測效能來講可以比合作式自相關接收機高出40％以上的偵測率，而在達成同樣偵測率的情況之下偵測點數更可比能量接收機少了有75%。
接著，在硬體設計中也提出了一個適用於此設計的新型快速傅立葉轉換器，為了有效的減少複雜的旋轉因子(Non-trivial Twiddler Factor)，我們採用了混和基搭配高基低分裂基Radix-2 and Radix-2/4/8/16 的拆解來降低運算雜度，多產生的特殊旋轉因子(Trivial Ttwiddle Factor)搭配了所提出的時間共享(Timing-Sharing)技術跟特殊常數取代法，如此一來即可用簡單的位移運算器跟加法器取代多數的常數乘法器，如此一來可有效率的節省電路面積。由於使用平行處理的架構，在記憶體模組上會有大量的需求，會造成面積及功率消耗的增加，搭配了所提出的暫存器交換式(Delay Buffer Change)可以提高蝴蝶運算器的使用效率，一組蝴蝶運算器即可對兩筆同時作處理，可以把吞吐率提高為兩倍，而且可以節省其中一塊記憶體的工作週期為50%，對於高點數的快速傅立葉轉換器可以有效率的節省功率消耗。
本偵測器電路採用了暫存器交換層級語言描述(RTL)，並且經由場效可程式閘陣列(FPGA)來完成驗證，最後由UMC90奈米製成，此偵測機晶片操作在100MHz之下總功率消耗為13.06(mw)，Core area為1585X1585(μm2)，此晶片總面積為2210 X 2210 (μm2)

In recent years, cognitive radio has become a valid solution to the problem of descrimination in the spectrum resource allocation. Among the categories of CR related technique, spectrum sensing is one of the most identical issues. Hence in this thesis, we present an optimal detector applied for the Thomson's adaptive multitaper spectral estimation (AMTSE) in CR. This detector is optimized based on Neyman-Pearson Theorem and it can adjust the detection thresholds to the environment change. In this way, the detector will be more robust to the colored noise impairments and be compatible to multiband spectrum sensing applications. The proposed AMTSE detector can greatly reduce the number of observations and detect the
primary users and spectrum holes compared with other conventional methods. It is shown that the detection rate of the proposed detector outperforms the one of energy detector by 40%. Besides, to achieve the PD = 0.999 the minimum required observation points of our proposed method are much fewer than the conventional one about 75%.
Subsequently, the author also proposes a novel FFT architecture for the AMTSE detector. The 1024 points FFT processor adopts the radix-2 and radix-2/4/8/16 to efficiently reduce the number of nontrivial twiddle factor multipliers. And by using the timing sharing techniques,
the trivial twiddle factor multiplier can be realized by using some adders and shifters. Moreover, we use delay buffer change technique to save power as only 0.06831(mw/MHz). The hardware complexity is significantly reduced that the gate count of FFT is 158.57 (gate/points)
and it is more efficient to handle two data streams. Finally, the proposed AMTSE detector has been emulated on the FPGA board and implemented with the synthesizable RTL by cell-based ASIC design flow. This chip is implemented in UMC 90-nm 1P9M process process, and the
power consumption of this detector operating in 100 MHz is 13.06 mw. The core area is 1585 × 1585(μm2) and the total area is 2210 × 2210(μm2).

1 Introduction 1
1.1 Background of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Cognitive Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Spectrum Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Main Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Review of Prior Spectrum Sensing Techniques 5
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Energy Detection Approach . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Matched-Filter Detection Approach . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Waveform-Based Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Autocorrelation-Based Detection . . . . . . . . . . . . . . . . . . . . . . . . 10
3 System Design 13
3.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Architecture Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1 Adaptive Multitaper Spectral Estimation (AMTSE) . . . . . . . . . . 15
3.3.2 Proposed Spectral Detector . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.3 System Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.4 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.5 Complexity Comparison . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 Simulation Results Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5 Word-length Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4 Hardware Design 43
4.1 specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2 Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.1 Fast Fourier Transform Algorithm . . . . . . . . . . . . . . . . . . . 44
4.2.2 Fast Fourier Transform Architecture . . . . . . . . . . . . . . . . . . 48
4.2.3 Proposed Fourier Architecture for AMTSE detecor . . . . . . . . . . 51
4.2.4 What Kinds of Decimation ? . . . . . . . . . . . . . . . . . . . . . . 51
4.2.5 What Kinds of radix ? . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.6 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3 AdaptiveWeighting Module . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.4 Comparison of Hardware resources . . . . . . . . . . . . . . . . . . . . . . 74
5 Implementation Results 85
5.1 FPGA Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1.1 FPGA feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1.2 Hardware Cost analysis . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.2 Post-Layout Simulation Result and Chip Layout . . . . . . . . . . . . . . . 90
5.2.1 Post-Layout Simulation . . . . . . . . . . . . . . . . . . . . . . . . 90
5.2.2 Power and Gate Count Analysis . . . . . . . . . . . . . . . . . . . . 92
5.2.3 Chip Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6 Conclusions and Future Works 97
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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