This paper presents a comprehensive fault-tolerant verification platform which can be used to characterize the impact of fault attribute on error coverage. The core of the verification platform is the scenario-based fault injection tool that can inject the transient and permanent faults into VHDL models of digital systems at chip, RTL and gate levels during the design phase. Weibull fault distribution is employed to decide the time instant of fault injection. A new feature of our tool is to offer users the statistical analysis of the injected faults. The statistical data for each injection campaign exhibit the degree of fault severity, which represents a fault scenario (or called fault environment). By varying the fault attributes, such as the fault duration or fault-occurring rate, we can produce a variety of fault scenarios for the fault simulations. Such simulations can reveal the error coverage of the fault-robust systems under various fault environments. Two case studies with experiments of fault injection were conducted to show how the fault attribute affects the error coverage.