A Scalable Split-Gate Flash Memory Cell Structure and Its Contactless Flash Memory Arrays

一種可微縮化分閘式快閃記憶細胞元結構及其無接點快閃記憶陣列

吳慶源(Ching-Yuan Wu)

《科學與工程技術期刊》 1卷1期 (2005/06) Pp. 5-16

https://doi.org/10.7117/JSET.200506.0005

摘要

本發明之一種可微縮化分閘式快閃記憶細胞元結構至少包含一個共源區、一個可微縮化分閘區藉由一個側邊牆介電墊層來形成、及一個可微縮化共源區，其中上述之可微縮化分閘區至少包含一個漂浮閘區藉由另一個側邊牆介電墊層來定義並具有一個尖形陰極線來擦洗。本發明的細胞尺寸係可微縮化且可以製造成等於4F^2或更小。上述之可微縮化分閘式快閃記憶陣列被用來組成兩種無接點快閃記憶陣列：一種無接點非或形快閃記憶陣列及一種無接點平行共源／汲導電位元線快閃記憶陣列以作為高速讀／寫／擦洗操作。另外，上述之無接點快閃記憶陣列比先前技術需要更少的嚴謹罩幕步驟來加予製造。

關鍵字

快閃記憶體 ； 分閘式 ； 側邊牆介電墊層 ； 無接點快閃記憶陣列 ； 嚴謹罩幕步驟 ； 漂浮閘

並列摘要

A scalable split-gate flash memory cell structure of the present invention comprises a common- source region. a scalable split-gate region formed by a sidewall dielectric spacer and a scalable common-drain region. wherein the scalable split-gate region comprising a floating-gate region being defined by another sidewall dielectric spacer has a tip-cathode line for erasing The cell size of the present invention is scalable and can be made to be equal to 4F^2 or smaller The structure is then used to implement two contactless flash memory arrays a contactless NOR-type flash memory array and a contactless parallel common-source/drain-conductive bit-lines flash memory array for high speed read/write/erase operations Moreover, the contactless flash memory arrays can be fabricated with fewer critical masking steps as compared to the prior art.

並列關鍵字

flash memory ； split-gate ； sidewall dielectric spacer ； contactless flash memory array ； critical mask steps ； floating gate