Performance Analysis of Enhanced Adaptive Logic Module for High Performance FPGA Architecture

V.J.K. Kishor Sonti ； Y. Varthamanan ； D. Sivaraman

《Research Journal of Applied Sciences, Engineering and Technology》 9卷3期 (2015/01) Pp. 215-223

並列摘要

The Enhanced Adaptive Logic Module for High Performance Field Programmable Gate Array Architecture has been designed to increase the speed and reduces the device utilization of FPGA Architecture. The existing altera based adaptive logic module has eight input critical path look up tables. That means six inputs are given directly to the one Lookup table and two inputs are given to the other LUT by shorting any two from the first LUT of that six inputs. So that the delays has been increased. The proposed EALM has 8 fracturable direct input LUT, so eight input logic function can be implement by using this module with high speed than the altera based ALM. In this method only one LUT is used and it produces single output. Thus there is no need of carry logic, so that the area has been reduced and increases the speed. And FPGA architecture is formed by combining four adaptive logic modules using programmable interconnect array. Enhanced adaptive logic module is introduced in that architecture instead of adaptive logic module and the performance is analyzed. The adaptive logic modules and enhanced adaptive logic modules of field programmable gate array architecture has been designed and simulated by using Xilinx ISE 12.1.

並列關鍵字

Adaptive logic module ； enhanced adaptive logic module ； field programmable gate array ； lookup table ； programmable interconnect array