一個應用於電力線通訊系統之10位元 動態元件匹配技術電流引導式數位類比轉換器

A 10-bit Current-Steering DAC with Dynamic Element Matching for Powerline Communication System

莊賀翔(He-Hsiang Chuang)

指導教授 ： 陳中平

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.00057

摘要

本論文提出一個適用於高解析度通訊系統的十位元數位類比轉換器。此數位類比轉換器應用於電力線通訊之類比前端接收發器中的傳送器，並達到電力線網路聯盟之最新規格(HomePlug AV2)。
為了改善靜態表現，本論文使用6 (thermometer-coded)-4 (binary-weighted)分段分時的編碼架構來達到良好匹配同時降低資料轉換時的突波。此外，我們亦使用四象限對稱方式來完成電流源陣列的設計；並加入假電晶體於陣列邊緣，降低位於陣列中心與邊緣之電流源間的誤差。針對動態表現方面，我們使用動態元件匹配技術[7][11][12]來提升線性度。
本晶片使用台積電90奈米互補式金氧半製程，晶片主動區域面積約0.35mm2。數位電路的電壓供應為1.2V，類比電路的電壓供給為1.2-V。最大的積分非線性誤差(INL)為-0.57LSB，最大的微分非線性誤差(DNL)為-0.44LSB。無雜散動態範圍(SFDR)在400MS/s之Nyquist取樣下為45dB。整體功率消耗為25.42mW。

關鍵字

數位類比轉換器 ； 電流引導式 ； 動態元件匹配技術 ； 電力線通訊

並列摘要

A 10-bit current-steering digital-to-analog converter (DAC) has been proposed for high accuracy communication systems. This chip is used for the transmitter (Tx) of the powerline communication (PLC) analog-front-end (AFE), and it reaches the standard of the HomePlug AV2 (2MHz~86MHz).
In order to improve static performance, we use 6(thermometer-coded)-4 (weighted) segmented decoding architecture to get good matching and reduce the glitch. Furthermore, we implement the current source array as common centroid and adding dummy current sources around the array to reduce the mismatch between edge and center. For dynamic performance consideration, the proposed DAC uses the Dynamic Element Matching (DEM) technique [7][11][12] to achieve good linearity.
The chip was fabricated in TSMC 90 nm CMOS technology and occupied 0.35 mm2 for active area. The supplies for the analog and digital circuits both are 1.2V. The maximum INL and DNL are -0.57 LSB and -0.44 LSB respectively. The SFDR is up to 45 dB for 400MS/s of Nyquist-rate sampling. The power consumption is 25.42mW.

並列關鍵字

DAC ； Current-steering ； DEM ； Powerline Communication

參考文獻

[2] Chi-Hung Lin and Klaas Bult “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998

[3] Santanu Sarkar , Swapna Banerjee “An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC” 2009 IEEE Computer Society Annual Symposium on VLSI

[5] Douglas A. Mercer, Member, IEEE “Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-m CMOS” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 8, AUGUST 2007

[6] Perter Palmers, Member, IEEE, and Michiel S. J. Steyaert, Fellow, IEEE” A 10-Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS” 2010 IEEE TRANSACTIONS ON CIRCUIT AND SYSTEM

[11] Da-Huei Lee, Tai-Haur Kuo, and Kow-Liang Wen “Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 2, FEBRUARY 2009