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  • 學位論文

應用於電力線通訊系統之管線式類比數位轉換器

Design of Pipelined ADC for PowerLine Communication System

指導教授 : 陳中平教授

摘要


管線式類比至數位轉換器一般被認為具有高速以及中高解析度的特性,並且被廣泛的應用於音訊處理、數位影像處理、影像壓縮以及通訊系統中。在本論文中提出了兩個使用不同架構,使用1.2伏特做為電源供應電壓的十位元管線式類比至數位轉換器,並且藉由台積電90奈米1P9M製程製造與量測。   為了達到高速的運算,我們在第一顆晶片使用每級解出1.5個位元的架構。運算放大器共享技巧被用來運算級中的放大器數目以降低功率損耗。除此之外,為了有效的降低後面運算級中放大器的增益以及頻寬規格,動態輸入範圍加倍的技巧也被運用在本晶片當中。在第二顆晶片中我們所使用的是每級解出2.5個位元的架構。為了達到取樣頻率200MS/s,我們將前端取樣與維持電路以及第一個使用動態輸入範圍加倍技巧的運算級合併成第一級的運算級。運算放大器共享技巧也被應用在本次設計當中用以降低功率損耗。最後,我們所設計的第一顆晶片也被應用在電力線通訊系統的類比前端電路當中。   在第一顆晶片的量測當中,其SNDR、SFDR以及ENOB分別為43.52dB,55.01dB以及6.94bit在取樣頻率以及輸入頻率分別為200MS/s以及1MHz之下,功率損耗是51.2毫瓦以及性能係數為2.08pJ/convstep。在第二顆晶片的量測中,其SNDR、SFDR以及ENOB分別為35.06dB,45.34dB以及5.53bit在取樣頻率以及輸入頻率分別為180MS/s以及1MHz之下,功率損耗是37.2毫瓦以及性能係數為4.47pJ/convstep

並列摘要


Pipelined Analog-to-Digital Converters (ADCs) are generally regarded as the ADCs with high speed and medium to high resolution characteristics. It has been widely utilized in audio signal processing, digital image processing, video compression and communication systems. This thesis presents two different architecture 10-bit CMOS Pipelined ADCs with supply voltage 1.2V. These two works are fabricated by TSMC 90nm 1P9M technology.   To achieve high conversion rate, the architecture used in the first chip is 1.5-bit/stage. In order to reduce power consumption, OP-amp sharing is introduced to reduce the amount of OP-amps used in the conversion stages. Moreover, we use dynamic-range-doubling (DRD) technique to halve the output swing of first conversion stage which can release the gain and bandwidth requirement of the OP-amps in the following stages. The architecture of second chip is 2.5-bit/stage. To achieve 200MS/s sampling rate, we merged the front-end sample-and-hold amplifier (SHA) and the first multiply DAC (MDAC) with 1.5-bit DRD architecture together as the first conversion stage. OP-amp sharing technique is also applied to this work to reduce power consumption. The first work is also applied to the analog front-end (AFE) of PowerLine Communication system.   According to the measurement results of first work with sampling rate 200MS/s and 1MHz input frequency, the SNDR, SFDR and ENOB achieves 43.52dB, 55.01dB and 6.94bit respectively. The power consumption is 51.2mW, and the FoM is 2.08pJ/convstep. In the second work with sampling rate 180MS/s and 1MHz input frequency, the SNDR, SFDR and ENOB achieves 35.06dB, 45.34dB and 5.53bit respectively. The power consumption is 37.2mW and FoM is 4.47pJ/convstep.

並列關鍵字

Pipelined ADC High Speed OP-amp sharing

參考文獻


[32] 林慶峰, “A High Speed and Low Power Pipelined ADC for Powerline Communication System,” Master Thesis, NTU, 2012
[13] Yingping Su, Ning Ning, Qi Yu, “A novel 2.5bit SHA-less MDAC design for 10bit 100Ms pipeline ADC,” 2011 International Conference on Computational Problem-Solving, pp.151-154, Oct. 2011.
[2] Findlater K., Bailey T., Bofill A., “A 90nm CMOS Dual-Channel Powerline Communication AFE for Homeplug AV with a Gb Extension,” IEEE Int. Solid-State Circuit Conf. (ISSCC)Dig. Tech. Papers, Feb 2008, pp. 464-628.
[3] B. Razavi, “Principles of Data Conversion System Design,” Wiley-IEEE Press, 1995.
[5] D. Johns and K. Martin, “Analog Integrated Circuit Design,” John Wiley & Sons, New York, 1997.

被引用紀錄


Ye, S. R. (2015). 應用於電力線通訊系統之低功耗OOK收發器暨HomePlug AV高速接收器 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342%2fNTU.2015.10025
Hsieh, M. H. (2015). 寬頻混合訊號與全數位延遲鎖相迴路暨HomePlug AV2電力線通訊系統收發器 [doctoral dissertation, National Taiwan University]. Airiti Library. https://doi.org/10.6342%2fNTU.2015.01854

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