一個單通道十位元四億赫茲導管式類比數位轉換器

A Single-Channel 10-bit 400-MS/s Pipeline ADC

徐振凱(Chen-Kai Hsu)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2015年)

https://doi.org/10.6342/NTU.2015.00029

摘要

類比數位轉換器是連接真實世界與離散運算領域的關鍵元件。
此篇論文提出了一個在九十奈米製程中實現的低功率管線式類比數位轉換器。然而放大器對於管線式類比數位轉換器來說，是一個非常重要且不可或缺的元件，另外為了使得管線式類比數位轉換器有良好的性能，放大器需要消耗相當可觀的功率消耗。管線式類比數位轉器使用n通道金氧半場效電晶體(NMOS)輸入，p通道金氧半場效電晶體(PMOS)為負載的單級放大器，已經在先前的成果[1]被證實，這種放大器可以提供更好的轉換效率。雖然這種放大器提升了功率效率，但是這種放大器帶來的負面效果是線性度的問題。在第一級解多位元是一個直接的解決辦法，然而這種做法會使得比較器的數目增加，並且對於比較器的偏移電壓容忍度更小。因此在此篇論文中，提出了粗級(coarse stage)輔助微級(fine stage)的概念。這種方式不僅僅在第一級解了四點五的位元而且也降低了比較器的數目，以及對於比較器的偏移電壓有更大的容忍度。
此次提出的類比數位轉換器已經於九十奈米製程中實現，核心電路所需要的晶片面積為0.15平方毫米。而此類比數位轉換器在一伏特的供給下，消耗了8.7毫瓦。實驗的結果顯示在輸入頻率為5.1-MHz下，信噪失真比(SNDR)約為57.23分貝，且在輸入頻率接近奈奎斯特頻率時，信噪失真比(SNDR)約為55.95分貝。另外在輸入頻率在整個奈奎斯特頻率的範圍內，信噪失真比(SNDR)皆高於55分貝。此篇論文的類比數位轉換器在每次轉換時所需要的能量約為42fJ。

關鍵字

高速 ； 低功耗 ； 管線式類比數位轉換器

並列摘要

Analog-to-digital (A/D) converters which have been a communicator between the analog world and digital domain are indispensable building block in many systems.
In this dissertation, a 10-bit 400-MS/s pipeline ADC is proposed to achieve low power in a 90-nm CMOS technology. On the other hand, amplifiers, important and indispensable block of pipeline ADCs, consume significant power to ensure the performance. A prior art [1] employing a single-stage amplifier consisting of a NMOS differential pair with a PMOS load in pipeline ADCs has been proved that amplifier can provide better conversion-efficiency while achieving better FoM. Although the amplifier increases the power-efficiency, it also introduces the ineluctable linearity issue. A multi-bit front-end stage is a straightforward solution but the solution increases the number of comparators and makes the front-end stage more sensitive to the offset. Hence, this work proposes a coarse-stage-assisted front-end stage that not only resolves 4.5-bit in the first stage but also reduces the number of comparators and becomes less sensitive to the offset.
The proposed ADC has been fabricated in a 90-nm standard CMOS technology which occupies 0.15mm2. The proposed ADC consumes 8.7 mW from a 1-V supply and achieves an SNDR of 57.23 dB at a 5.1-MHz input and 55.95 dB near Nyquist rate. It also achieves a signal-to-noise-plus-distortion (SNDR) better than 55 dB over the entire Nyquist band. The figure-of-merit (FoM) of the proposed ADC is 42 fJ/Conv.

並列關鍵字

High-speed ； low-power ； pipeline ADC

參考文獻

[1]B. Sahoo and B. Razavi, “A 10-b 1-GHz 33-mW CMOS ADC,” IEEE J. of Solid-State Circuits, vol. 48, no. 6, pp. 1442-1452, Jun.2013.

[2]B. N. Fang and J. T. Wu, “A 10-bit 300-MS/s pipelined ADC with digital calibration and digital bias generation,” IEEE J. of Solid-State Circuits, vol. 48, no. 3, pp. 670-683, Mar. 2013.

[3]D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, New York, 1997.

[4]F. Maloberti, Data Converters, Springer, Dordrecht, 2007.

[5]M. Gustavsson, J. J. Wikner, and N. Tan, CMOS Data Converters for Communi -cations, Kluwer Academic Publisher, Boston, 2000.