適用於物聯網系統之可編譯低延遲密碼協同處理器

Programmable Low-Latency Crypto-Coprocessor for Machine-to-Machine System

蕭名群(Ming-Chun Hsiao)

指導教授 ： 吳安宇

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.10040

摘要

本篇論文提出一應用以處理器為基礎設計的多模式(包含NTRU、TTS、Pairing)公開金鑰密碼學(PKC)演算法之硬體實現。可視為針對應用高強度硬體輔助設計之PKC於物聯網系統資料安全系統中跨出的一大步。藉由供應、運算、維持、一般管理中大幅度降低成本的現象和傳統認為PKC在物聯網中的感應器太過耗費資源的問題形成強烈對比。除此之外，相對於對稱性基礎演算法，PKC演算法需要極為少的金鑰交換管道而達到低耗能的結果。因此，我們最主要目標在於設計適用於物聯網系統應用之以處理器為基礎的PKC引擎.
在這篇著作中發表一具低延遲與可編譯性之加解密協同處理器。包含了硬體架構的設計和對應的指令集設計。為了能達到低延遲之效果，平行處理密碼學運算之特定的運算單元變得不可或缺，除此之外，在加解密協同處理器中運用智慧型的管理機制能達到48%的加速效果。在指令集的部分，多面相的指令設計讓擴展其使用時的彈性限制，而系統管理的指令，如迴圈控制指令，對整體效能提升甚有幫助。最重要的是，我們所提出的協同處理器能透過主人端與僕人端的通道在SoC的系統中進行驗證。在台積電90奈米的製程中，針對所提出的協同處理器的晶片中，整個晶片在200MHz的頻率下，其大小為1.40毫米乘1.40毫米，其中核心的尺寸為0.92毫米乘0.81毫米。為了能夠達到進一步的系統晶片驗證，我們採用了CIC所提供的MorPACK平台來完成可編譯邏輯器的實現與晶片在真實SoC系統的驗證。

關鍵字

密碼學 ； 物聯網

並列摘要

We present an ASIP implementation of multi-mode public-key cryptosystems (PKCs), including NTRU, TTS, and Pairing. It represents the first step toward securing machine-to-machine (M2M) systems using strong, hardware-assisted PKC. In contrast to the conventional wisdom that PKC is too “expensive” for M2M sensors, it actually can lower the total cost of ownership because of cost savings in provision, deployment, operation, maintenance, and general management. Furthermore, PKC can be more energy-efficient because PKC-based security protocols usually involve less communication than their symmetric-key-based counterparts, and communication is getting relatively more and more expensive compared with computation. Therefore, our primary goal is to design the feasible ASIP-based PKC design to provide general data security in M2M applications.
In this thesis, the low-latency and programmable crypto-coprocessor is proposed, including architecture and instruction design. For the purpose of the low-latency, specific computation unit is special-designed for parallelization. Moreover, intelligent control mechanism is involved to improve the overall performance by 48%. The corresponding instruction set design is also proposed. Multi-phase instructions enhance the overall flexibility. Other system-level instructions, such as loop control also enhance the overall performance. Most important of all, the proposed design can be placed on SoC platform for system verification, with one master port and one slave port. At last, the low-latency and programmable crypto-coprocessor at TSMC 90 nm is implemented, with the 0.92mm x 0.81mm core area and 1.40mm x 1.40mm chip area at the frequency of 200MHz. For further silicon verification, the MorPACK platform from the CIC is adopted for FPGA emulation and chip verification in real SoC system.

並列關鍵字

Cryptography ； Machine to machine

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