以壓控振盪器為基礎且具平移平均之三角積分調變器

The Design and Analysis of a Shifted-Averaging VCO-Based Delta-Sigma Modulator

康毓軒(Yu-Hsuan Kang)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.00285

摘要

本論文呈獻一個基於壓控震盪器的三階連續時間三角積分調變器。以壓控震盪器為基礎的量化器具有開迴路一階雜訊調變以及閉迴路天生動態加權平均等好處，但是輸入電壓對輸出頻率的非線性仍然是個必須解決的問題。這篇論文提出了一個平移平均的方法來延展線性操作區間，並且將調變器中的前饋加法器以及迴路延遲補償皆整合至壓控震盪器當中，節省了額外的硬體並減少消耗功率。本晶片使用台積電六十五奈米互補式金氧半製程所實現，在十六億赫茲的取樣頻率下操作，並於兩千萬赫茲的有效頻寬下得到65.2 dB的訊號雜訊失真比以75.4 dB的訊號無雜散比。在1.2伏特的電源供應下總共消耗21.1毫瓦，所佔晶片面積只有0.159平方毫米。

關鍵字

壓控震盪器 ； 三角積分調變器

並列摘要

This thesis presents a third-order continuous-time delta-sigma modulator with a VCO-based quantizer. A VCO-based quantizer possesses attractive characters of open-loop first-order noise-shaping and barrel-shifting output code when used as closed-loop. However, the non-linear nature of the voltage-to-frequency tuning curve is still a problem to be solved. A shifted-averaging linearization technique is proposed and a modulator with the proposed technique is fabricated in TSMC N65 GP+ 1P6M technology. Aside from the linearization technique, the feed-forward voltage summer and excess loop delay compensation are both integrated into the VCO quantizer, which saves power and area. The prototype modulator is operated at 1.6GHz sampling clock. It achieves peak SNDR of 65.2dB and peak SFDR of 75.4dB within 20MHz bandwidth. The chip dissipates 21.1mW from a 1.2V supply. The active area of this modulator occupies only 0.159mm2.

並列關鍵字

vco ； delta-sigma modulator

參考文獻

[1] M. Park, A 4th Order Continuous-Time ΔΣ ADC with VCO-Based Integrator and Quantizer, PhD thesis, 2009.

[3] M. Z. Straayer and M. H. Perrott, “A 12-bit, 10-MHz Bandwidth, Continuous-Time ΔΣ ADC with a 5-bit, 950-MS/s VCO-based Quantizer,”IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805–814, Apr. 2008.

[4] M. Park and M. Perrott, “A 0.13 μm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based Integrator and Quantizer,” in IEEE Int. Solid-State Circuits Conf., 2009, pp. 170–171.

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