使用分時多工時間數位轉換器具量化雜訊消除技巧操作於三十六億赫茲之小數型全數位鎖相迴路

A 3.6-GHz Quantization Noise Cancellation Fractional-N ADPLL using Time-Division Multiplexing TDC

盛允楨(Yun-Chen Sheng)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.00260

摘要

本篇論文實現了一個具量化雜訊消除功能的全數位小數型鎖相迴路。本鎖相迴路操作在三十六億赫茲，使用了分時多工時間數位轉換器以偵測量化雜訊消除增益。利用量化雜訊消除技巧，可以將三角積分調變器所產生的量化雜訊消除。在傳統做法上，需要利用一增益校正迴路以校正消除增益，鎖相迴路的鎖定時間會因此增加。利用所提出之分時多工時間數位轉換器，消除增益可被快速且精確的計算出來，且不會影響鎖定時間。
此量化雜訊消除技巧實現於一個36億赫茲頻帶的全數位鎖相迴路。使用台積電90奈米製程，整個系統操作於1.2 V，共花費8.16 mA電流，核心電路面積為0.329 mm2。在三十六億赫茲下，所量測到的參考突波為 -45 dBc。相位雜訊於10 MHz 頻率偏移下從 -99 dBc/Hz 改善為-123 dBc/Hz，有23dB的改善。由10 kHz積分到40 MHz的均方根抖動從10.88 ps改善為4.605 ps。量測到的全數位鎖相迴路的鎖定時間為6 μs。

關鍵字

全數位小數頻率合成器 ； 量化雜訊 ； 時間數位轉換器 ； 鎖相迴路

並列摘要

A 3.6-GHz quantization noise cancellation fractional-N ADPLL using time-division multiplexing time-to-digital converter (TDM TDC) is presented. With quantization noise cancellation technique, quantization noise from delta-sigma modulator (DSM) can be greatly reduced. In a conventional approach, a gain calibration loop is adopted to estimate cancellation gain factor, and thus PLL lock time is degraded. With the proposed TDM TDC, no gain calibration is required. TDM TDC achieves fast and accurate cancellation gain estimation, and PLL lock time is not degraded as that of a conventional approach.
The proposed technique is implemented in the design of a 3.6-GHz ADPLL. Fabricated in the TSMC 90-nm CMOS technology, the whole system dissipates 8.16 mA from a 1.2-V supply and the active area is 0.329 mm2. At 3.6 GHz, the reference spur at 26 MHz offset is -45 dBc and the phase noise measured at 10-MHz offset is reduced from -99.79 dBc/Hz to -123.44 dBc/Hz, corresponding to 23-dB improvement. RMS jitter integrated from 10 kHz to 40 MHz is reduced from 10.88 ps to 4.605 ps. The measured lock time of the proposed ADPLL is 6 μs.

並列關鍵字

ll-Digital Fractional-N Frequency Synthesizer ； Quantization Noise ； Time-to-Digital Converter ； Phase-Locked Loop

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