以65-nm CMOS 製程製作應用於背板通訊之有線收發器

Wireline Backplane Transceivers in 65-nm CMOS Technology

施育男(Yu-Nan Shih)

指導教授 ： 李致毅

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.10093

摘要

在本文中，我們將會介紹三個以65-nm CMOS 製程製作的有線背板電路系統，包括10 Gb/s 的決策回饋等化器、20 Gb/s 的收發器以及40 Gb/s 的收發器。
在10 Gb/s 的決策回饋等化器中，他包含了一個類比等化器和一個有可適應性迴路的決策回饋等化器。這個晶片在以211−1 PRBS 的編碼下，可以走FR4 這種板材的傳輸線80 公分，並且達到位元誤碼率小於10−12。此外，這個電路在1 伏特的操作電壓下，消耗31 毫瓦，晶片面積則為0.1 平方公厘。
在20 Gb/s 的收發器中，我們在傳輸端製作了27-1 PRBS 產生器、注入式鎖相迴路和前饋等化器，在接收端則有一可適應性的類比等化器以及資料時脈回復電路。這個系統可以傳輸在60 公分的FR4 板材下達到位元誤碼率小於10−13，並且在傳輸端操作電壓1.2 伏特的情況下消耗310 毫瓦、接收端操作電壓1.3 伏特的情況下消耗190 毫瓦，而晶片面積在傳輸端與接收端分別為0.27 平方公厘和0.32平方公厘。
在40 Gb/s 的收發器中，我們在傳輸與接收端都使用延遲線架構的前饋等化器，其中在接收端的前饋等化器還有一個可適應性迴路。我們把這組晶片安置在羅捷士RO 4003 這種板材上，在27−1 PRBS 的編碼下可以傳遞20 公分。傳輸端在操作電壓為1.2 伏特的情況下消耗135 毫瓦、接收端在操作電壓為1.6 伏特的情況下消耗322 毫瓦，而晶片面積在傳輸端與接收端分別為0.63 平方公厘和0.66 平方公厘。

關鍵字

決策回饋等化器 ； 有線背板收發器 ； 鎖相迴路資料時脈回復電路前饋等化器

並列摘要

In this thesis, three wireline backplane circuit systems will be demonstrated, including a 10 Gb/s Decision Feedback Equalizer (DFE), a 20 Gb/s Transceiver Chip-set, and a 40 Gb/s Transceiver Chip-set. They are all implemented in 65-nm CMOS Technology.
First of all, in 10 Gb/s Decision Feedback Equalizer, it consists of an analog equalizer and a decision feedback equalizer with an adaptation loop. This circuit achieves BER < 10−12 for 211−1 PRBS in 80 cm FR4 channel, and consumes 31 mW with 1 V supply. Besides, the chip area is less than 0.1 mm2.
In 20 Gb/s Transceiver Chip-set, a 27−1 PRBS generator, an injection-locked PLL, and a 3-Tap feed-forward equalizer (FFE) are implemented in transmitter side. An adaptive analog equalizer and CDR are implemented in receiver side. This system achieves BER < 10−13 in a 60 cm FR4 channel, and consumes 310 mW and 190 mW with 1.2 V and 1.3 V supply in transmitter and receiver, respectively. The chip occupies 0.27 mm2 in transmitter and 0.32 mm2 in receiver.
Finally, in 40 Gb/s Transceiver Chip-set, we propose a delay-line-based feed-forward equalizer in both transmitter and receiver, and an adaptation loop is implemented in receiver. We mount transmitter and receiver chip on Rogers RO 4003 board with 20 cm transmission line, and the chip-set can achieve BER < 10−12 for 27−1 PRBS. This chip-set occupies 0.63 mm2 in transmitter and 0.66 mm2 in receiver, and consumes 135 mW with 1.2 V supply and 322 mW with 1.6 V in transmitter and receiver, respectively.

並列關鍵字

Decision Feedback Equalizer (DFE) ； Wireline Backplane Transceiver ； PLL ； CDR ； Feed-Forward Equalizer (FFE)

參考文獻

[2] Universal Serial Bus：http://www.usb.org/

[6] Jri Lee, “A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 41, no. 9, pp. 2058-2066, Sep. 2006.

[7] M. E. Austin, “Decision-feedback Equalization for Digital Communication over Dispersive Channels,” Tech. Rep. 437, MIT Lincoln Lab, Lexington, MA, August 1967.

[8] James E. C. Brown et al., “A 35 Mb/s Mixed-Signal Decision-Feedback Equalizer for Disk Driver in 2-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 31, no. 9, pp. 1258-1266, Sep.1996.

[9] Vladimir Stojanovic et al., “Autonomous Dual-Mode (PAM2/4) Serial Link Transceiver With Adaptive Equalization and Data Recovery,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 1012-1026, Apr.2005.