應用於早期預防心因性猝死之系統演算法及架構設計

Algorithm and Architecture Design for Sudden Cardiac Death Prevention System

鄭吏芳(Li-Fang Cheng)

指導教授 ： 陳良基

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.00511

摘要

心因性猝死(Sudden Cardiac Death, SCD)是當今社會主要的非自然死因之一。儘管現今的醫療照護技術持續的進步，心因性猝死的死亡率依然居高不下。如何預防心因性猝死的發生，一直是醫學研究上的一大挑戰。近來已有臨床醫學的報告指出，若能將心因性猝死早期徵兆的偵測結果即時提供給患者，可解決大部分患者延遲就醫的問題，並改善其預後結果。因此，提供使用者一具備即時反映心臟狀況與偵測危險徵兆的系統，對於早期預防心因性猝死將是一大幫助，而我們選擇透過心電訊號的處理來達到這個目標。心電圖(electrocardiogram, ECG)是醫學上常用的非侵入式診斷工具，它可以用來觀察心臟狀況，並作為許多心臟疾病的診斷依據，包括心因性猝死的早期徵兆，也被認為可藉由心電圖的處理與觀察得知。由於許多心因性猝死的早期徵兆是不定期出現的，想要增加這些徵兆的偵測率，就必須長時間持續觀察心電圖。現今的Holter系統可提供24小時的心電圖紀錄功能，但是此類系統不易攜帶，提供給使用者的功能也是有限的。近年來興起的體表感測器網路(body area sensor network, BASN)則可無線傳輸生理訊號，大幅降低感測裝置的體積。然而，在實際應用方面，如何降低此類系統的功耗，以及建立多功能即時處理平台將是一大挑戰。

在此篇論文中，我們將設計一基於心電圖訊號處理的心因性猝死預防系統，並分為兩大部份來研究。在第一階段的研究中，我們主要開發心因性猝死的預防演算法，可實現兩種主要功能:心因性猝死的偵測(detection)與預測(prediction)。在偵測功能的部分，主要包含心律不整(arrhythmia)與急性冠狀動脈症狀(acute coronary syndrome, ACS)的偵測。我們定義並測試偵測演算法的主要步驟，包括心電圖的濾波器設計、波形描繪與特徵值萃取。由於偵測演算法的開發已較為成熟，我們主要專注開發長期性預測心因性猝死的演算法。我們所提出的演算法，主要由長期性特徵值萃取與機器學習的技術構成，並於MIT-BIH所提供的標準心電圖資料庫上驗證。初步研究結果發現，若結合傳統的心律變化率(heart rate variability, HRV)與QTc等特徵值，分辨心因性猝死與正常個體的辨識率可達到90%以上。我們更進一步提出基於小波轉換能量的特徵值，可將辨識率提高至95%。然而受限於目前可用的資料庫規模，此演算法未來仍需持續地使用更多個體資料做驗證。

在第二階段的研究上，我們根據演算法的特性，以及低功耗與高彈性度的系統要求，設計並實作一多功能心電圖處理器來實現心因性猝死的預防系統。在架構設計上，我們主要採用多重異質性的處理單元來因應多功能系統要求，處理流程則可分為四個管線化處理階段。根據每個階段運算複雜度的差異，我們設計了兩種處理單元作為運算核心。首先，我們設計加速器來最佳化運算量較高的功能區塊，包含有限脈衝響應濾波器、連續性小波轉換與多重特徵值萃取。此外，我們整合多核心的系統架構來增加系統的彈性度。藉由雙向通用管線化處理單元的設計，傳統多核心系統的匯流排衝突率可被有效降低，而系統功耗則可削減85%左右。最後，藉由加速器與通用管線化處理器的結合，可實現多重訊號處理功能，相較於之前所提出的系統，我們所提出的系統彈性度與擴充能力是大幅增加的。

最後，在系統實作上，我們採用時脈門控與電壓縮放的技術進一步降低50%的系統功耗。根據晶片的量測結果，我們的系統能以54.3微瓦(μW)的功耗條件，實現高準度心律不整與急性冠狀動脈症狀的單通道偵測。相較於之前所提出的系統架構，在同樣低於100微瓦的功耗條件下，此架構設計可提供更高階的訊號處理功能，並具有更高的系統彈性度。因此我們認為，此架構設計可滿足心因性猝死預防系統所需具備的即時處理、低功耗等需求。

關鍵字

預防心因性猝死 ； 體表感測器網路 ； 連續性小波轉換 ； 機器學習 ； 低功耗多核心處理器

並列摘要

Among all causes of death, the Sudden Cardiac Death (SCD) is one of the most leading causes in current society. Although increasing efforts have been done in clinical care, the survival rates of SCD still remain low. The prevention of SCD may be one of the most challenging problems. According to recent clinical reports, early reminder of SCD events, such as fatal arrhythmias and myocardial infarction can reduce the delay to search for medical service and improve the clinical outcomes of individuals. Therefore, the design of a system that can reflect the cardiac status and provide real-time warning for the users should be helpful for early prevention of SCD. The electrocardiogram (ECG) is a powerful non-invasive clinical tool for the observation of cardiac status and the diagnosis of cardiac diseases. Through the screening of ECG signals, the discovery of the pre-SCD syndromes is considered to be possible. Because the occurrences of cardiac syndromes are aperiodic, long-term monitoring is often required to increase the possibility of abnormality detection. Current Holter ECG devices can provide ECG signal recording for about 24 hours, but the form factor issue and the insufficient functionality for the users weaken the feasibility of the device. The emerging body area sensor network (BASN) provides a wireless solution to minimize the size of the ECG monitor. However, how to reduce the power consumption and simultaneously provide versatile functions to cope with the syndromes of interest in real-time is a challenge for the designers.

In this thesis, we aim to design a SCD prevention system based on ambulatory ECG signal processing. In the first part, the design of algorithms for SCD prevention is studied and proposed. Two major functions are taken into considerations for the prevention system--the SCD detection and prediction. The detection function is designed to provide arrhythmia detection and acute coronary syndrome (ACS) detection. The basic functional blocks required to realize the SCD detection function are tested and defined, including signal filtering, ECG delineation and feature extraction. Since several accurate algorithms have been proposed for these functions, we then focus on the exploration of the challenging problem about long-term SCD prediction. In this thesis, the algorithm adopting multiple long-term ECG features and the support vector machine (SVM) technique is developed and evaluated through the standard MIT-BIH ECG databases. Through combining conventional features of HRV and corrected QT interval (QTc), the positive prediction rate (PPV) is reported to be above 90% for the classification of high-risk SCD patients and normal subjects when testing on the standard MIT-BIH databases. We further propose the usage of time-frequency scalogram features, and the PPV over 95% can be reached. Since the number of available database is limited, the algorithm should be further verified on larger databases.

In the second part of the thesis, a versatile ECG processor (VECGP) with high functional flexibility and low power consumption is designed and implemented in order to meet the requirements of the SCD prevention system. We propose the system architecture that is composed of heterogeneous processing units. Totally four pipeline stages are arranged in the proposed architecture, which are responsible for the four sequential processing stages of the proposed integrated SCD prevention algorithm. According to the computation complexity of the functional blocks of the algorithm, two different types of processing units are proposed for the system. Three accelerators--the finite impulse response (FIR) filtering module, two-scale continuous wavelet transform (CWT) module, and the integrated feature extraction engine (IFEE) are designed and implemented for system optimization. On the other hand, we explore the integration of multi-core architecture into our system for flexibility enhancement. Based on the non-uniform memory access (NUMA) architecture, the two-way pipeline processing unit (PPU) is designed to relieve the bus conflict problem that a multi-core system may encounter when performing pipeline processing flows. About 85% of power reduction is achieved compared with the traditional symmetric multiprocessing (SMP) system. Through the integration of accelerators and PPUs, a variety of processing modes for different application scenarios can be realized.

Finally, the proposed architecture is implemented by UMC 90nm low-leakage process with 40 MHz as the maximum operating frequency. We further adopt the clock gating and voltage scaling techniques to reduce 50% of the system dynamic power. According to our measurement results, the chip can perform the ACS detection, arrhythmia detection and classification functions with only 54.3 μW for single-channel ECG processing. Compared with previous work, both the flexibility and versatility of the system are improved with sub-100 μW power consumption. Therefore, we consider that the proposed architecture meets the goals of a low-power ambulatory ECG processing system for SCD prevention application.

並列關鍵字

sudden cardiac death prevention ； body area sensor network ； continuous wavelet transform ； machine learning ； low-power multi-core processor

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