- 學位論文
無線區域網路 自動增益控制電路之設計與實作
Design and Implementation of an Automatic Gain Control Circuit for Wireless LAN
摘要
自動增益控制為一個能夠自動調整放大器增益並提供固定振幅輸出的系統。在通訊系統中，保持信號強度在一個合理的範圍是一件很重要的事情。所以，在此論文中，我們提出了一個新的架構，使電路能夠在三個時脈周期中，調整增益並得到固定振幅。我們都知道射頻訊號在空氣傳播常常會為雜訊所影響。所以信號強度可能會從-90 dBm變化至-10 dBm。因此我們不僅需要一個大動態範圍的射頻前端電路，也需要一個自動增益電路來保持信號強度。 此論文展現了一個應用於IEEE 802.11a, b, g的自動增益控制電路的設計與實作。 此自動增益控制系統包含了四級串接的可變增益放大器，峰值偵測器，五位元類比數位轉換器以及數位控制電路。我們提出了一個具有直流偏差消除且快速鎖定的混合信號自動增益控制電路。此系統是利用台灣積體電路公司0.25微米1P5M CMOS製程來設計，以達到小尺寸、低必v消耗、高可靠度的目標。其中的可變增益放大器可以提供2~20 dB的可變範圍。我們並使用內建低通濾波器來解決直流偏移的問題。在我們的設計中，直流偏差可以忍受超過10 mV，而峰值偵測器的操作頻率超過100 MHz，已符合802.11的規格（54 MHz）。此外，所有的數位電路皆用Verilog-XL設計且驗證，並用Apollo完成佈局。整個系統也利用Cadence中的SpectreVerilog做模擬，以証明電路能夠快速鎖定，以符合系統規格。
並列摘要
Automatic gain control (AGC) is a system that can automatically adjust the gain of an amplifier to maintain constant signal strength. In the communication system, it is very important to keep signal strength in a reasonable magnitude. So, in this Thesis, we propose a new architecture to adjust gain and get the constant output within three clock cycles. We all know that the RF signals are affected by the interference and blocked by wall when they are transmitted in the air. The signal strength will vary form -90 dBm up to -10 dBm. So we not only need a wide dynamic range RF front-end circuit but also require an AGC to maintain the signal strength. This Thesis presents the design and implementation of an automatic gain control (AGC) for Wireless LAN in 802.11a, b, and g system. The AGC system consists of four cascaded VGA’s, a Peak Detector (PD), a 5-bit Analog-to-Digital Converter (ADC), and a Digital Controller. We proposed a fast-settled mixed-mode AGC with DC offset cancellation. The AGC system is designed in TSMC 0.25μm 1P5M CMOS process to achieve a small size, low power consumption, minimum external parts, and high reliability design. The VGA has a variable gain range from 2 to 20 dB. We use a built-in LPF to solve the DC offset problem, and the DC offset tolerance can be up to 10 mV. The PD can operate up to 100 MHz which satisfies already the 802.11 specifications (54 MHz). And then, since the 5-bit flash ADC operates only in 2 MHz, we can minimize the power consumption. All the digital circuits are designed using Verilog-XL and layout using Apollo. The whole system is simulated and verified using Cadence SpectreVerilog.