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  • 學位論文

運用可適性網格方法之階層式電容抽取

Robust and Hierarchical capacitance extraction using adaptive meshing

指導教授 : 陳中平

摘要


在ULSI奈米設計的尺寸中,其不斷增加的複雜度,對於寄生的電容抽取有越來越大的挑戰,所以就次微米設計的結構裡,關於延遲時間的快速估計需要有效並且準確的電容計算。而計算導體連結之結構的許多應用程式裡,其中以階層式邊界元素法來做數值分析的計算,可以大大節省許多運算時間以及記憶體的消耗,但是在面電荷密度的計算,卻會造成其不穩定以及不正確。因為在某些情況,對於階層式結構的網格方法,發現在此種切割的結構底下(e.g.鄰邊結構),誤差不收斂的問題,以及在計算邊界上點電荷的數值,特別是在角落的部分。 當我們想要分析導體之網格越切越細微,其電荷量加總值會越來越大,但是增加的幅度會趨於收斂,所以我們利用這樣的特性,去計算由ICCAP的三維電容抽取方法,所產生出來的稀疏細數矩陣,來達到更有效率並且更準確。

並列摘要


The ever-increasing complexity of nano-scale ULSI design has made parasitic capacitance extraction more and more challenging. Efficient and accurate capacitance calculation is needed urgently for delay evaluation especially for deep sub-microndesigns. With the wide-spread application of interconnect structure, the boundary element method based for the structure of hierarchical discretization, although it significantly increases the execution time and memory consumption, but also gives rise to instability and inaccuracy during the surface charge density calculation. Because in some situation for the panel refinement of hierarchical structure, we can find under the structure of subdivion, the error estimation is not convergence, and to considerate the value of point discharge on the side of boundary, especially on the corner. When the panel refinement of interconnect which we want to analysis is subdivided finer and finer, and the total charge increase more and more, but the percentage of increase will be convergence. This thesis presents ICCAP to determine the precision due to the charge difference, which increase is convergence while the panel refinement is fine enough, further getting the adaptive meshing to solve the sparsified potential coefficient matrices which be derived from ICCAP for three-dimensional capacitance extraction. to be more efficient and accuracy.

參考文獻


[1] K. Nabors and J. White. Fastcap: a multipole accelerated 3-d capacitance extraction program. IEEE Trans. on CAD, pages 1447–1459, 1991.
[2] J. Tausch and J. White. A multiscale method for fast capacitance extraction. Proc. DAC, pages 537–542, 1999.
[3] The International Technology Roadmap for Semiconductors (2001).
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[6] S. Yan, V. Sarin, and W. Shi. Sparse transformations and preconditioners for hierarchical 3-d capacitance extraction with multiple dielectrics. Proc. DAC, pages 788–793, 2004.

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