用於影像處理及智能操作之可重組化影像處理器

隨著半導體產業的蓬勃發展，影像感測器(CMOS/CCD Sensor)的解析度快速增加，對嵌入式影像處理器造成沉重的運算負擔。同時越來越多手持式裝置上都配備了影像感測器。因此，在這些設備上對影像處理的需求的應用範圍越來越廣泛。對於嵌入式影像處理器而言，它必須處理高品質影像且擁有低功率消耗的特性以延長電池使用時間，再加上其功能必須富有彈性以應付各種設備上不同的應用。也就是說：千萬畫素以上的影像處理能力並且滿足不同使用者的需求。對於這樣高度運算強度以及高度彈性的使用需求，高效率的處理器是必須存在以面對這類問題。處理能力(Performance)與使用彈性(Flexibility)分別代表影像處理器需求的兩個極端，造成架構設計上的取捨(Trade-off)考量。在論文中，首先分析了在數位相機或手持式攝影機中的影像處理程序(Image Processing Pipeline)以及其操作模式。針對此應用的設計挑戰(Design Challenge)在此歸納。其次，現今存在的各種解法與策略將在此分析，針對其所選擇的處理能力與使用彈性之取捨，分別做出其優缺點之討論。為達到足夠之使用彈性與處理能力要求，本論文中簡介相關演算法之研究與整理結論。更高強度的影像處理演算法及更高使用彈性之智能操作(Intelligent Operation)演算法造成更高的運算能力需求。在考慮相關演算法之需求後，本論文之設計動機將被提出以滿足其設計挑戰。用於影像處理及智能操作之可重組化影像處理器(CRISP-II)之架構設計包含三個主要部分：處理器之控制架構、資料存取部分以及資料處理部分。多資料流(Multi-stream)模式之統一標準協定架構，此架構之設計用於各種不同可重組化元件之間的重組能力。這些不同的可重組化元間之間的資料傳輸與操作需要統一的協定，而此多資料流模式更提供了其所需的使用彈性。階層式環狀(Hierarchical Ring)互連網架構用於處理器中的資料存取部分。環狀互連網(Ring-based Interconnection)之分析，說明了其提供足夠的使用彈性。更進一步降低其互連複雜度後，連線造成之硬體成本跟著下降。各種可重組化處理元件(Reconfigurable Stage Processing Element)代表了處理器之資料處理部分。這些可重組化處理元件達成影像處理以及智能操作之處理能力要求。其中，樹狀架構之資料流處理器(Tree-based Stream Processor)在此被提出，其處理能力使得此處理器能夠完成智能操作中必須之自適運算(Adaptive Computation)。用於影像處理及智能操作之可重組化影像處理器的原型晶片以TSMC 90nm之製程實作，其晶片實作結果包含於本論文中。為處理更複雜之影像處理程序，本處理器將以各方面之比較來展現其處理能力與使用彈性之優點。對於下一世代之影像處理應用的支援與展示會與前幾代的可重組化影像處理器做比較。而其功率消耗效率(Power Efficiency)的表現，將在與近年最先進之影像處理器比較中，強調其對於處理能力與使用彈性之平衡點取捨。此處理器適合用於目標之影像處理程序，其處理能力可完成高度的運算強度需求，而其足夠的使用彈性將能滿足下一代數位相機及手持式攝影機的各類應用需求。

關鍵字

可重組化影像處理器；粗顆粒；可重組化架構；影像處理器；數位相機

並列摘要

As the advances in semiconductor technology, the resolutions of CMOS/CCD sensors grow dramatically, which introduces heavy computational loading for the embedded image processing tasks. On the other hand, there are more and more handheld devices being equipped with image sensors. Therefore, the demand of image processing increases for various applications on these devices. For an embedded image processor, it is required to process high-quality images with long battery-endurance, and the functionality should be flexible for different applications and devices: it should have at least 10 mega-pixel processing capability, and meet different preferences of users. For this high computationally intensity and high flexibility needs, a highly efficient processor is essentially required. The performance and flexibility stand for the two-end requirements of image processors, which results the trade-off consideration in architecture design. First, this thesis analysis the image processing pipelines for different operation modes of digital still cameras (DSCs) and camcorders. The design challenges of performance and flexibility requirement is then concluded. Second, the strategy of existing solutions would be analyzed to show the pros and cons by considering the relationship of performance and flexibility. For achieving the sufficient flexibility and performance requirements, survey summary of related algorithms is introduced in this thesis. The enhancement of image processing algorithms and more flexible applications with intelligent operations make the demands of computing ability higher and higher. Motivation of this thesis is further proposed to fulfill the design challenges with the consideration of related algorithms. Architecture design of coarse-grained reconfigurable image stream processor for image-processing and intelligent operations (CRISP-II) includes three main parts: the control scheme of processor, the data-accessing part, and data-operating part. Multi-stream mode unified protocol architecture is made for the reconfiguration of several different reconfigurable elements. The data transfer and operation between the reconfigurable elements require the unified protocol, and multi-stream mode provides the flexibility demand. Hierarchical ring architecture is introduced for data-accessing part of processor. With the ring-based interconnection analysis, the architecture has sufficient flexibility. By complexity reduction of interconnection, hardware cost on wire-load is further decreased. The data-operating part includes several kinds of reconfigurable stage processing element (RSPE), which achieve performance requirement and required processing ability of image-processing and intelligent operations. A tree-based stream processor is proposed in this thesis for adaptive computation, which is the essential part of intelligent operations. The prototype chip of CRISP-II is implemented by TSMC 90nm technology, and the VLSI implementation result is shown in thesis. For more complex pipelines, this processor shows its ability of performance and flexibility with several comparisons. The advance of the processor for future applications is demonstrated in the comparison with previous CRISP processors. The power efficiency comparison with other state-of-the-art processors highlights the trade-off selection of CRISP-II processor, which is suitable for target applications with higher performance for high computation intensity and sufficient flexibility for the image processing pipelines in DSCs and camcorders.

並列關鍵字

CRISP-II ； CRISP ； coarse-grained ； reconfigurable architecture ； image stream processor ； digital still camera ； image-processing

參考文獻

[2] W. Rabadi, R. Talluri, K. Illgner, J. Liang, and Y. Yoo, “Programmable DSP platform for digital still cameras,” Application Report, Apr. 2000.

[3] J. Zhou, “Getting the most out of your image-processing pipeline,” White Paper, Texas Instruments, May 2008.

[5] W.-C. Kao, S.-H. Wang, L.-Y. Chen, and S.-Y. Lin, “Design considerations of color image processing pipeline for digital cameras,” IEEE Trans. Consumer Electronics, vol. 52, no. 4, pp. 1144-1152, Nov. 2006.

[6] J. C. Chen and S.-Y. Chien, “Crisp: Coarse-grained reconfigurable image stream processor for ten mega pixels for digital still cameras,” M.S. thesis, Department of Electronics Engineering, National Taiwan University, Taiwan, 2006.

[8] W. Rabadi, R. Talluri, K. Illgne, J. Liang, and Y. Yoo, “Programmable DSP platform for digital still cameras,” in Proc. 1999 IEEE International Conference on Acoustics and Speech and Signal Processing (ICASSP99), Mar. 1999, pp. 2235 – 2238.

國際替代計量

用於影像處理及智能操作之可重組化影像處理器

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