數位分數階微分器及積分器之設計

The Design of Digital Fractional-order Differentiators and Integrators

范雅婷(Ya-Tin Fan)

指導教授 ： 貝蘇章

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.10095

摘要

本文介紹一些常見的數位微積分器及分數階微積分器。第二到四章介紹三種積分的數值方：Newton-Cotes quadrature rule, Gauss-Legendre quadrature rule 和 Clenshaw-Curtis quadrature rule。伴隨這些數值方而來的小數週期元件就利用一些已熟知的小數週期延遲濾波器，例如: FIR Lagrange 和IIR allpass fractional delay filters來做IIR數位積分器的設計。我們用圖形比較以上設計的優缺點並提出一個合併的設計。第五章我們用一系列的方法來設計分數階微積分器。先是比較一些連續輸入數位化， 轉換的方法；其次利用二項展開或連分數展開，使得分數階可以化成整數階。利用最小平方誤差的方法來降低錯誤率。我們比較不同方法的頻率響應上的錯誤率以及在相位上的表現。並且，我們討論這些濾波器的特性。最後第六章，我們做一些整理和建議未來可以繼續研究的方向。

關鍵字

數位積分器 ； 數值積分法 ； 分數階微積分器 ； 數位化 ； 數位微分器 ； 連分數展開

並列摘要

In this thesis, we introduce a few designs of digital integrator, and a few designs of fractional-order differintegrator. We apply some numerical integration rules and fractional delay filters to obtain the closed form design of IIR digital integrators. There are three types of numerical integration rules to be investigated: Newton-Cotes quadrature rule, Gauss-Legendre quadrature rule and Clenshaw-Curtis quadrature rule. The fractional delay involved in the design will be implemented by FIR Lagrange and IIR allpass fractional delay filters. Also, a combined version is proposed. Several digital filter design examples are illustrated to demonstrate the effectiveness. Chapter 5 is to show the designs of the fractional-order differintegrator. We find a suitable generating function to fit the ideal fractional-order differintegrator. Then discretize the fractional-order with a power series expansion or continued fraction expansion. Last, we discuss the different methods to decrease the absolute magnitude error. Moreover, the filter properties will also be presented at the end of the chapter. Finally, we make a conclusion of this thesis and suggest the future work in chapter 6.

並列關鍵字

Digital integrator ； Numerical integration rule ； fractional-order differintegrator ； Discretization ； Digital differentiator ； Continued fraction expansion

參考文獻

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