應用於無線壓阻感測器之前端電路與超再生接收機設計

Design of Front-end Circuits and a Super-Regenerative Receiver for Wireless Piezoresistive Sensing Applications

蕭博允(Po-Yun Hsiao)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.01079

摘要

本作品中實踐了一個應用於無線壓阻感測器之前端電路設計以及操作於四億赫茲且是低功率消耗之超再生接收機。
提出的應用於壓阻式感測器之前端電路中，採用一振盪器將電阻的資訊轉成頻率資訊，並使用一混頻器將頻率降頻到低頻做解調。降頻等效上為一時間上的放大器，讓系統對於電阻的靈敏度更好。為了在感測前讓混頻器的輸出頻率固定，振盪器從較高的頻率慢慢校正至與參考頻率固定的一頻率。此前端電路是使用台積電0.35微米製程設計，振盪器頻率設計為24 MHz、校正後混波器輸出頻率為100 kHz、整體消耗功率為1 mW、電阻的靈敏度為7 kHz/Ohm.
提出的超再生接收機使用三角積分調變器的原理去解調接收到的訊號，以改善傳統解調器解析度收到參考時脈的限制。另外提出了一快速頻率校正的機制運用逐步逼近法的原理將接收機中振盪器的頻率在12個參考週期內校正到所想要的頻段，即400 MHz。此接收機是使用台積電0.18微米製程設計，消耗功率為1.37 mW、接收器的靈敏度為-50 dBm，當接收1 Mbps的訊號時，能源效益為 1.37 nJ/bit，頻率校正的時間為2.5 ns。

關鍵字

壓阻感測器 ； 超再生接收機 ； 快速頻率校正 ； 三角積分脈衝解調器

並列摘要

In this work, the front-end circuit and a 400-MHz super-regenerative receiver for piezoresistive sensing applications are implemented.
The proposed front-end circuit for piezoresistive sensor composes an oscillator to transfer the resistance information into frequency domain and a mixer to down-convert the frequency to lower frequency for digitizing the resistance information. The down-conversion operation is an amplifier in time domain which can increase the system sensitivity to resistance variation. To calibrate the output frequency of mixer before sensing, the oscillation frequency is tuned from the maximum frequency to fix the difference with the reference frequency. The front-end circuit is fabricated in a TSMC 0.35-mm CMOS technology. The oscillation frequency is 24 MHz; the output frequency of mixer is 100 kHz. The total front-end circuit consumes 1 mW with 3-V supply. The system sensitivity is 7 kHz/Ohm
The proposed super-regenerative receiver adopts the theorem of delta-sigma modulator to demodulate the received signal to improve the limitation of the conventional demodulator. A fast frequency calibration is also proposed by the meaning of SAR algorithm to regulate the oscillation frequency to the specific frequency band, 400 MHz. The receiver is fabricated in TSMC 0.18-mm CMOS technology. It consumes 1.37 mW with 1-V supply. The system sensitivity is -50 dBm. The energy efficiency is 1.37 nJ/bit with 1-Mbps input signal. The calibration time is 250 ns.

並列關鍵字

Piezoresistive sensor ； Super-regenerative receiver ； fast frequency calibration ； Delta-Sigma pulse-width demodulator

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