快速鎖定與低雜訊之鎖相迴路設計

Design of Fast-Settling and Low-Noise Phase-Locked Loops

邱威豪(Wei-Hao Chiu)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2011年)

https://doi.org/10.6342/NTU.2011.01080

摘要

於許多電路系統當中，鎖相迴路系統通常是不可或缺的一重要元件，其作為電路系統中的重要頻率訊號來源，以供應穩定且精確之頻率給予整體系統；依據不同之操作特性，鎖相迴路可被區分為兩種型態，即整數型鎖相迴路與小數型相迴路，此兩種型態之鎖相迴路可在不同需求下被選擇使用，然而這兩種型態之鎖相迴路亦有各自之缺點；對於整數型鎖相迴路而言，其參考頻率受限於所需要之通道頻寬，此致使於窄通道頻寬之系統應用中，整數型鎖相迴路將被迫使用低參考頻率與低迴路頻寬，造成鎖定時間變慢之問題。此外，於小數型鎖相迴路中，為了產生更高頻率解析度而產生之量化雜訊，同樣也造成了寬頻寬設計之困難處。於本篇論文中，將針對此兩種鎖相迴路型態之問題進行探討，並且提出相應之技術解決其缺點，提升整體效能。首先，對於整數型鎖相迴路，本篇論文提出了動態相位誤差補償之技術，此一技術增速了鎖定過程，使迴路能夠操作在如同寬頻鎖相迴路下之鎖定速度；接下來，針對小數型鎖相迴路中之量化雜訊影響問題，本篇論文提出一量化雜訊移動架構，能夠將迴路中之調變行為自原迴路中分離出來，因此可引用額外的調變參數來降低調變時所產生之量化雜訊。
此兩種技術皆以台積電0.18深次微米金氧半導體製程(TSMC 0.18µm CMOS)進行實作，其量測結果驗證了所提出技術之改善效能。在整數型鎖相迴路當中，若於20-kHz與40-kHz之窄頻寬下啟用所提出之動態相位誤差補償技術，其鎖定時間能夠改善至於10微秒(10µs)內鎖定頻率；而於小數型鎖相迴路中，所提出之量化雜訊移動架構得到了改善效果上之證明，由於自原迴路中被分離出之解調動作已不再基於迴路參數進行調變，是故調變之過程改由額外設計之參數影響，量化雜訊與小數突波得以降低，在所給予之設計參數下，量化雜訊之改善超過30dB，並且在小數突波上也有超過10dB的改善。

關鍵字

鎖相迴路 ； 快速鎖定 ； 量化雜訊

並列摘要

Phase-locked loops (PLL) are the key component in various systems. According to the operated principles, there are two different PLL types, the integer-N PLL and the fractional-N PLL. Both types are employed under different environments, but each type suffers from the different design tradeoffs. For the integer-N PLL, the selectable reference frequency is associated with specific channel spacing. It then suffers from narrow loop bandwidth when demanding narrow channel spacing, degrading the frequency-settling time. Next, for the fractional-N PLL, it is known that the tradeoff between the quantization noise and the loop bandwidth is always a concern. To address this issue, in this dissertation, two techniques are proposed to enhance both the integer-N PLL and fractional-N PLL. First, this dissertation proposes a fast-settling technique, dynamic phase error compensation, to speed up the settling process. In addition, this dissertation also proposes a quantization-noise-shifting architecture for the fractional-N PLL, which separates the modulation path from the original loop. This allows independent parameter design to lower the quantization noise while employing wide loop bandwidth.
Both techniques were fabricated in TSMC 0.18-µm CMOS. Measured results verify the proposed techniques that effectively improve the performance for each PLL type. For the integer-N PLL with 20-kHz and 40-kHz loop bandwidth, the settling time is faster than 10µs. For the fractional-N PLL, via the proposed quantization noise shifting architecture, it effectively reduces the quantization noise and fractional spurs. The measurement demonstrates that more than 30-dB suppression on quantization noise is reached, furthermore, more than 10-dB improvement for fractional spurs is also achieved.

並列關鍵字

Phase-Locked Loops ； Fast-Settling ； Quantization noise

參考文獻

[1] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000.

[3] F. Gardner, "Charge-pump phase-lock loops," IEEE Trans. on Communications, vol.28, pp. 1849- 1858, Nov. 1980.

[4] M. Van Paemel, "Analysis of a charge-pump PLL: a new model," IEEE Trans. on Communications, vol.42, pp.2490-2498, July 1994.

[5] M. Bayer, T. Chomicz, F. James, P. McEntarfer, D. Mijuskovic, and J. Porter, "A low noise CMOS frequency synthesizer with dynamic bandwidth control," IEEE CICC, pp. 171-174, Sep. 1994.

[6] C. Vaucher, "An adaptive PLL tuning system architecture combining high spectral purity and fast settling time," IEEE J. Solid-State Circuits, vol.35, pp. 490-502, Apr. 2000.