- 學位論文
以硝酸氧化備製中堆疊高介電常數氧化鉿閘極介電層之金氧半電容元件特性研究
Investigation of HfO2 High-k Gate Dielectrics in Tandem Structure Fabricated by Nitric Acid Oxidation for MOS Devices
摘要
本論文為探討以堆疊結構成長高介電常數閘極介電層之電流與電容特性比較。首先在 P 型基板上利用純水陽極氧化技術於室溫生長超薄二氧化矽作為初始緩衝層,經退火處理後再利用濺鍍法鍍上鉿薄膜並利用硝酸氧化技術形成氧化鉿。 第一個實驗我們比較三種不同介電層形式的樣本,分別是純二氧化矽氧化層(等效厚度 EOT 約 2.1nm)、二氧化矽堆疊一層氧化鉿(~2.9nm)以及二氧化矽堆疊兩層氧化鉿(~3.8nm)。我們發現隨著堆疊層數的增加,其在負偏壓情況下的閘極漏電流呈現下降趨勢,比較經過連續兩次氧化鉿堆疊製備前後元件特性,其閘極漏電流大幅下降了 7 個數量級之多,也具備良好的電容電壓特性曲線。考慮去除厚度對電流的影響因素後,我們比較了相同等效電場下的漏電流,發現堆疊結構的確大幅改善了氧化層的品質。我們推斷在堆疊結構下的元件具有隨意分散的介面缺陷密度使得氧化層本質漏電流路徑可被有效的阻擋。對照電容電壓特性曲線,發現介面缺陷密度會隨堆疊層數增加而增加。分析三種樣品的均勻性,以固定電流下的電壓變化來看,發現其均勻性也隨著堆疊層數增加而更加改善。這說明了氧化層品質可以藉由分層堆疊方式將其單層不均勻性的影響減到最小。接下來的實驗,我們將這三片樣本放置在 380 °C氮氣環境下進行熱退火,此舉可有效去除介電層中的氫或其他帶電的離子。經過熱退火後,除了純二氧化矽介電層的樣本外,其他樣本的平帶電壓與介面陷阱密度都大幅減少,代表熱退火對於修復高介電常數介電層的品質來說是必要的。
並列摘要
In this work, the electrical and capacity characteristics of HfO2 high-k gate dielectric in tandem structure are investigated. The ultrathin interfacial SiO2 grown on p-type Si substrate was prepared by anodization in D.I water followed by post oxidation anneal. The sputtered hafnium film was oxidized by diluted nitric acid (HNO3) to form the HfO2 dielectric layer. First, we compared three kinds of MOS capacitors, i.e., the pure SiO2 dielectrics (EOT~2.1nm), one HfO2 dielectric stacked on SiO2 dielectrics (EOT~2.9nm) and two HfO2 dielectrics stacked on SiO2 dielectrics (EOT~3.8nm). We found that the gate leakage current in negative voltage bias decreased with the stacked layer added more. The gate leakage current value in tandem structure sample was scaled down about seven orders difference compared to the sample without tandem structure fabrication and it still showed good electrical and capacitance characteristics. Excluding the effect of dielectric thickness, we found that the dielectrics fabricated in tandem structure obviously improved the quality of oxide dielectrics according to the leakage current of the equivalent electric field. We proposed that the devices in tandem structure have random distributed defect which could block the path of intrinsic current conduction. The fact that the interfacial defect density became more when stacked layer was added was observed from the capacitance voltage characteristic curve. The uniformity of these three samples also improved as the stacked layer added in terms of the voltage at specific current value, which illustrated that this separated stacked fabrication could largely reduce the influence of nonuniformity in each monolayer. In the following experiment, these three samples were annealed in 380 ℃ N2 ambient which could eliminate the hydrogen and other ions. Through this annealing, the flat band voltage and interfacial defect density was largely decreased in all samples except the pure SiO2 sample. It proved that the post metallization anneal is necessary for high-k dielectric to repair.