降低時脈抖動敏感度之連續時間型三角積分調變器設計

Design of Continuous-Time Delta-Sigma Modulator with Reduced Sensitivity to Clock Jitter

張育誠(Yu-Cheng Chang)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.10274

摘要

在目前中高速的應用上，採用連續時間型三角積分調變器作為類比數位轉換器是一個相當好的選擇。然而，連續時間型的三角積分調變器的效能，易受到真實電路先天的非理想效應影響，包含了內部迴路延遲和時脈抖動等因素。真實電路的操作時間造成的迴路延遲，會使三角積分調變器迴路系統不穩定，或是降低訊號雜訊比(SNR)。而時脈抖動的影響，主要來自回授路徑上的數位類比轉換器(DAC)所貢獻。時脈抖動會調變DAC的回授波型，貢獻雜訊到訊號輸入端。此貢獻的雜訊因與輸入信號同路徑進入系統，因此不受雜訊移頻(noise shaping)的抑制，而降低三角積分調變器的效能。
本文提出一個多階波型回授的方式，去降低時脈抖動的影響性。用經過延遲串列和數位邏輯運算的時脈去控制DAC作回授。用此方法，不但可以有效降低時脈抖動的影響，而且不需要花過多額外的功率消耗。此方法還有較不受遲電路的非理想效應影響的好處。對於迴路延遲的影響，本文利用簡單的電路技巧，改善傳統的迴路延遲補償方法。不但可以有效解決迴路延遲造成的問題，又可以不需要採傳統方式所需的加法器
為驗證提出的方法。本文利用上述技巧，並採用台積電0.18微米互補式金氧半製程，實現了一個三階一位元連續時間型三角積分器。其使用400 MHz的取樣頻率在4MHz的頻寬下，可以得到69dB的訊號雜訊比和71dB的動態範圍。使用1.8伏的供應電源時，需要消耗19毫瓦的功率。此連續時間三角積分調變器適合使用於無線接收機系統之中。

關鍵字

連續時間型三角積分器 ； 類比數位轉換器 ； 雜訊移頻 ； 迴路延遲 ； 時脈抖動

並列摘要

For medium data rate applications, the continuous-time (CT) delta-sigma modulator is an appropriate candidate for implementing the ADC. However, the CT delta-sigma modulator is known to be sensitive to the excess loop delay (ELD) in the modulator and the clock jitter. Finite circuit response time causes latency in the modulator loop, which corrupts the modulator stability and degrades the system signal-to-noise ratio (SNR). On the issue of the clock jitter, the main culprit arises from the feedback DAC. The clock jitter modulates the DAC feedback waveforms and in effect adds noise to the input signal. Such noise content, just as the input signal, is not subject to the high-pass noise-shaping of the loop; thus, it directly results in SNR reduction.
This work proposes a simple technique to reduce clock jitter effects that shapes the DAC feedback waveform as multi-step fixed-ON RZ. The sampling clock is processed by delay chain and digital logic to control the feedback DAC. By this way, this technique can reduce the clock jitter effect effectively but also archive low penalty of power consumption and delay element non-linearity. On the ELD issue, we use a digital circuit technique to improve the conventional ELD compensation technique that is necessary to a summing amplifier.
To validate the proposed technique, a 3rd –order single-bit CT delta-sigma modulator is implemented in the TSMC 0.18-mm 1P6M COMS process. The proposed modulator achieves a 69-dB peak SNR with a 4-MHz bandwidth at a 400-MHz sampling rate and has an 71-dB dynamic range. The implemented modulator consumes 19mW from a 1.8-V supply. The proposed continuous-time delta-sigma modulator is suitable for wireless wideband systems.

並列關鍵字

Continuous-time delta-sigma modulator (CTDSM) ； analog–to-digital convertor (ADC) ； noise shaping ； excess loop delay (ELD) ； clock jitter

參考文獻

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