透過您的圖書館登入
IP:3.236.64.8
  • 學位論文

應用於遠距醫療照護之離散時間式接收機前端電路

Discrete-Time Receiver Front-End for Remote Healthcare Applications

指導教授 : 汪重光

摘要


得利於半導體與移動科技的蓬勃發展,元件大小與功率消耗不斷下降。單一元件整合越來越多的功能,實現一個遠距醫療照護系統晶片不再遙不可及。無線接收機為遠距醫療照護系統中不可或缺的元件之一,其主要任務為在醫生與病患之間處理接收到的生理信號。如同大部分的可攜式元件,功率消耗將是在無線接收機設計上最重要的考量之一。因此,此論文將主要著重於低功率消耗無線接收機前端電路的設計與實現。 首先在低雜訊放大器的設計上,此論文提出具雙路雜訊抑制機制之低雜訊放大器架構,藉以同時達到低功率消耗與高可靠度。在傳統的雜訊抑制架構上加上轉導激勵技術,此具雙路雜訊抑制機制之低雜訊放大器將可以達到十分貝的單端順向增益、三點七分貝的雜訊指數以及八分貝毫瓦的三階輸入截止點,並且在一伏特的單一電壓供應下,核心元件只消耗一點二毫瓦的功率。除此之外,此具雙路雜訊抑制機制之低雜訊放大器也保有傳統雜訊抑制架構的優點,如:平衡非平衡轉換與利用轉導值的輸入阻抗匹配。 整體接收機則是採用離散時間方式來實現。此論文所提出之次取樣濾波器可以對信號同時進行降頻、濾波與離散時間化。整體的接收機前端具有十一點八分貝的含緩衝器單端增益、二十六點七分貝的含緩衝器雜訊指數以及負十五分貝毫瓦的三階輸入截止點。在一伏特的單一電壓供應下,核心元件只消耗三點八毫瓦的功率。

並列摘要


Thanks to semiconductor and mobile technology developments, device size and power consumption keep scaling down. More and more functions are integrated into one device now. Realizing a remote healthcare system on a single chip is no longer a fantasy. One of most important devices in a remote healthcare system is wireless receiver, which is responsible to deal with the received vital data between doctors and patients. Just like most portable devices, power consumption is always a major design concern. Thus, this thesis will focus on the low power wireless receiver design. In the low noise amplifier design, a dual-path noise-cancelling architecture is proposed to achieve low power consumption and high reliability simultaneously. The dual-path noise-cancelling low noise amplifier utilizes the noise-cancelling architecture combined with the gm-boosting technique, which achieves 10dB single-ended forward gain, 3.7dB noise figure and 8dBm input 3rd-order intercept point with only 1.2mW core power consumption and a single 1.0V supply voltage. The dual-path noise cancelling low noise amplifier also exhibits excellences of noise-cancelling architectures, such as balance- unbalance transformation and 1/gm matching. Furthermore, the discrete-time receiver architecture is adopted. The subsampling filter is proposed to downconvert, filter and discretize signal simultaneously. Whole receiver front-end achieves 11.8dB single-ended conversion gain with buffer loss, 26.7dB noise figure with buffer noise, and -15dBm 3rd-order intercept point with only 3.8mW core power consumption and a single 1.0V supply voltage.

參考文獻


[1] Department of Health, Executive Yuan, R.O.C.. (2011, July 15). 99年度死因統計完整統計表 [XLS]. Available: http://www.doh.gov.tw/.
[9] M. Khanpour, K. W. Tang, P. Garcia and S. P. Voinigescu, “A wideband w-band receiver front-end in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 43, no. 8, pp. 1717-1730, August 2008.
[6] N. J. Oh and S. G. Lee, “Building a 2.4-GHz radio transceiver using IEEE 802.15.4,” IEEE Circuits and Devices Magazine, vol. 21, no. 6, pp. 43-51, January 2006.
[7] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts and B. Nauta, “Wideband balun-LNA with simultaneous output balancing, noise-canceling and distortion-canceling,” IEEE Journal of Solid-State Circuits, vol. 43, no. 6, pp. 1341-1350, June 2008.
[8] C. S. Wang, J. W. Huang, K. D. Chu and C. K. Wang, “A 0.13μm CMOS fully differential receiver with on-chip baluns for 60GHz broadband wireless communications,” in IEEE Custom Integrated Circuits Conference, San Jose, California, September 2008, pp. 479-482.

延伸閱讀